1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3228-cru.h> 8#include <dt-bindings/thermal/thermal.h> 9#include <dt-bindings/power/rk3228-power.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 serial0 = &uart0; 19 serial1 = &uart1; 20 serial2 = &uart2; 21 spi0 = &spi0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@f00 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <0xf00>; 32 resets = <&cru SRST_CORE0>; 33 operating-points-v2 = <&cpu0_opp_table>; 34 #cooling-cells = <2>; /* min followed by max */ 35 clock-latency = <40000>; 36 clocks = <&cru ARMCLK>; 37 enable-method = "psci"; 38 }; 39 40 cpu1: cpu@f01 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a7"; 43 reg = <0xf01>; 44 resets = <&cru SRST_CORE1>; 45 operating-points-v2 = <&cpu0_opp_table>; 46 #cooling-cells = <2>; /* min followed by max */ 47 enable-method = "psci"; 48 }; 49 50 cpu2: cpu@f02 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a7"; 53 reg = <0xf02>; 54 resets = <&cru SRST_CORE2>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 #cooling-cells = <2>; /* min followed by max */ 57 enable-method = "psci"; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 resets = <&cru SRST_CORE3>; 65 operating-points-v2 = <&cpu0_opp_table>; 66 #cooling-cells = <2>; /* min followed by max */ 67 enable-method = "psci"; 68 }; 69 }; 70 71 cpu0_opp_table: opp-table-0 { 72 compatible = "operating-points-v2"; 73 opp-shared; 74 75 opp-408000000 { 76 opp-hz = /bits/ 64 <408000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 opp-suspend; 80 }; 81 opp-600000000 { 82 opp-hz = /bits/ 64 <600000000>; 83 opp-microvolt = <975000>; 84 }; 85 opp-816000000 { 86 opp-hz = /bits/ 64 <816000000>; 87 opp-microvolt = <1000000>; 88 }; 89 opp-1008000000 { 90 opp-hz = /bits/ 64 <1008000000>; 91 opp-microvolt = <1175000>; 92 }; 93 opp-1200000000 { 94 opp-hz = /bits/ 64 <1200000000>; 95 opp-microvolt = <1275000>; 96 }; 97 }; 98 99 arm-pmu { 100 compatible = "arm,cortex-a7-pmu"; 101 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 106 }; 107 108 psci { 109 compatible = "arm,psci-1.0", "arm,psci-0.2"; 110 method = "smc"; 111 }; 112 113 timer { 114 compatible = "arm,armv7-timer"; 115 arm,cpu-registers-not-fw-configured; 116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 118 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 120 clock-frequency = <24000000>; 121 }; 122 123 xin24m: oscillator { 124 compatible = "fixed-clock"; 125 clock-frequency = <24000000>; 126 clock-output-names = "xin24m"; 127 #clock-cells = <0>; 128 }; 129 130 display_subsystem: display-subsystem { 131 compatible = "rockchip,display-subsystem"; 132 ports = <&vop_out>; 133 }; 134 135 i2s1: i2s1@100b0000 { 136 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 137 reg = <0x100b0000 0x4000>; 138 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 139 clock-names = "i2s_clk", "i2s_hclk"; 140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 141 dmas = <&pdma 14>, <&pdma 15>; 142 dma-names = "tx", "rx"; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&i2s1_bus>; 145 status = "disabled"; 146 }; 147 148 i2s0: i2s0@100c0000 { 149 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 150 reg = <0x100c0000 0x4000>; 151 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 152 clock-names = "i2s_clk", "i2s_hclk"; 153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 154 dmas = <&pdma 11>, <&pdma 12>; 155 dma-names = "tx", "rx"; 156 status = "disabled"; 157 }; 158 159 spdif: spdif@100d0000 { 160 compatible = "rockchip,rk3228-spdif"; 161 reg = <0x100d0000 0x1000>; 162 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 164 clock-names = "mclk", "hclk"; 165 dmas = <&pdma 10>; 166 dma-names = "tx"; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&spdif_tx>; 169 status = "disabled"; 170 }; 171 172 i2s2: i2s2@100e0000 { 173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 174 reg = <0x100e0000 0x4000>; 175 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 176 clock-names = "i2s_clk", "i2s_hclk"; 177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 178 dmas = <&pdma 0>, <&pdma 1>; 179 dma-names = "tx", "rx"; 180 status = "disabled"; 181 }; 182 183 grf: syscon@11000000 { 184 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; 185 reg = <0x11000000 0x1000>; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 189 io_domains: io-domains { 190 compatible = "rockchip,rk3228-io-voltage-domain"; 191 status = "disabled"; 192 }; 193 194 power: power-controller { 195 compatible = "rockchip,rk3228-power-controller"; 196 #power-domain-cells = <1>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 200 power-domain@RK3228_PD_VIO { 201 reg = <RK3228_PD_VIO>; 202 clocks = <&cru ACLK_HDCP>, 203 <&cru SCLK_HDCP>, 204 <&cru ACLK_IEP>, 205 <&cru HCLK_IEP>, 206 <&cru ACLK_RGA>, 207 <&cru HCLK_RGA>, 208 <&cru SCLK_RGA>; 209 pm_qos = <&qos_hdcp>, 210 <&qos_iep>, 211 <&qos_rga_r>, 212 <&qos_rga_w>; 213 #power-domain-cells = <0>; 214 }; 215 216 power-domain@RK3228_PD_VOP { 217 reg = <RK3228_PD_VOP>; 218 clocks =<&cru ACLK_VOP>, 219 <&cru DCLK_VOP>, 220 <&cru HCLK_VOP>; 221 pm_qos = <&qos_vop>; 222 #power-domain-cells = <0>; 223 }; 224 225 power-domain@RK3228_PD_VPU { 226 reg = <RK3228_PD_VPU>; 227 clocks = <&cru ACLK_VPU>, 228 <&cru HCLK_VPU>; 229 pm_qos = <&qos_vpu>; 230 #power-domain-cells = <0>; 231 }; 232 233 power-domain@RK3228_PD_RKVDEC { 234 reg = <RK3228_PD_RKVDEC>; 235 clocks = <&cru ACLK_RKVDEC>, 236 <&cru HCLK_RKVDEC>, 237 <&cru SCLK_VDEC_CABAC>, 238 <&cru SCLK_VDEC_CORE>; 239 pm_qos = <&qos_rkvdec_r>, 240 <&qos_rkvdec_w>; 241 #power-domain-cells = <0>; 242 }; 243 244 power-domain@RK3228_PD_GPU { 245 reg = <RK3228_PD_GPU>; 246 clocks = <&cru ACLK_GPU>; 247 pm_qos = <&qos_gpu>; 248 #power-domain-cells = <0>; 249 }; 250 }; 251 252 u2phy0: usb2phy@760 { 253 compatible = "rockchip,rk3228-usb2phy"; 254 reg = <0x0760 0x0c>; 255 clocks = <&cru SCLK_OTGPHY0>; 256 clock-names = "phyclk"; 257 clock-output-names = "usb480m_phy0"; 258 #clock-cells = <0>; 259 status = "disabled"; 260 261 u2phy0_otg: otg-port { 262 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-names = "otg-bvalid", "otg-id", 266 "linestate"; 267 #phy-cells = <0>; 268 status = "disabled"; 269 }; 270 271 u2phy0_host: host-port { 272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "linestate"; 274 #phy-cells = <0>; 275 status = "disabled"; 276 }; 277 }; 278 279 u2phy1: usb2phy@800 { 280 compatible = "rockchip,rk3228-usb2phy"; 281 reg = <0x0800 0x0c>; 282 clocks = <&cru SCLK_OTGPHY1>; 283 clock-names = "phyclk"; 284 clock-output-names = "usb480m_phy1"; 285 #clock-cells = <0>; 286 status = "disabled"; 287 288 u2phy1_otg: otg-port { 289 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "linestate"; 291 #phy-cells = <0>; 292 status = "disabled"; 293 }; 294 295 u2phy1_host: host-port { 296 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 297 interrupt-names = "linestate"; 298 #phy-cells = <0>; 299 status = "disabled"; 300 }; 301 }; 302 }; 303 304 uart0: serial@11010000 { 305 compatible = "snps,dw-apb-uart"; 306 reg = <0x11010000 0x100>; 307 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 308 clock-frequency = <24000000>; 309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 310 clock-names = "baudclk", "apb_pclk"; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 313 reg-shift = <2>; 314 reg-io-width = <4>; 315 status = "disabled"; 316 }; 317 318 uart1: serial@11020000 { 319 compatible = "snps,dw-apb-uart"; 320 reg = <0x11020000 0x100>; 321 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 322 clock-frequency = <24000000>; 323 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 324 clock-names = "baudclk", "apb_pclk"; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&uart1_xfer>; 327 reg-shift = <2>; 328 reg-io-width = <4>; 329 status = "disabled"; 330 }; 331 332 uart2: serial@11030000 { 333 compatible = "snps,dw-apb-uart"; 334 reg = <0x11030000 0x100>; 335 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 336 clock-frequency = <24000000>; 337 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 338 clock-names = "baudclk", "apb_pclk"; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&uart2_xfer>; 341 reg-shift = <2>; 342 reg-io-width = <4>; 343 status = "disabled"; 344 }; 345 346 efuse: efuse@11040000 { 347 compatible = "rockchip,rk3228-efuse"; 348 reg = <0x11040000 0x20>; 349 clocks = <&cru PCLK_EFUSE_256>; 350 clock-names = "pclk_efuse"; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 354 /* Data cells */ 355 efuse_id: id@7 { 356 reg = <0x7 0x10>; 357 }; 358 cpu_leakage: cpu_leakage@17 { 359 reg = <0x17 0x1>; 360 }; 361 }; 362 363 i2c0: i2c@11050000 { 364 compatible = "rockchip,rk3228-i2c"; 365 reg = <0x11050000 0x1000>; 366 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 clock-names = "i2c"; 370 clocks = <&cru PCLK_I2C0>; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&i2c0_xfer>; 373 status = "disabled"; 374 }; 375 376 i2c1: i2c@11060000 { 377 compatible = "rockchip,rk3228-i2c"; 378 reg = <0x11060000 0x1000>; 379 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 clock-names = "i2c"; 383 clocks = <&cru PCLK_I2C1>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&i2c1_xfer>; 386 status = "disabled"; 387 }; 388 389 i2c2: i2c@11070000 { 390 compatible = "rockchip,rk3228-i2c"; 391 reg = <0x11070000 0x1000>; 392 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 clock-names = "i2c"; 396 clocks = <&cru PCLK_I2C2>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&i2c2_xfer>; 399 status = "disabled"; 400 }; 401 402 i2c3: i2c@11080000 { 403 compatible = "rockchip,rk3228-i2c"; 404 reg = <0x11080000 0x1000>; 405 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 clock-names = "i2c"; 409 clocks = <&cru PCLK_I2C3>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&i2c3_xfer>; 412 status = "disabled"; 413 }; 414 415 spi0: spi@11090000 { 416 compatible = "rockchip,rk3228-spi"; 417 reg = <0x11090000 0x1000>; 418 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 422 clock-names = "spiclk", "apb_pclk"; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; 425 status = "disabled"; 426 }; 427 428 wdt: watchdog@110a0000 { 429 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; 430 reg = <0x110a0000 0x100>; 431 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&cru PCLK_CPU>; 433 status = "disabled"; 434 }; 435 436 pwm0: pwm@110b0000 { 437 compatible = "rockchip,rk3288-pwm"; 438 reg = <0x110b0000 0x10>; 439 #pwm-cells = <3>; 440 clocks = <&cru PCLK_PWM>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pwm0_pin>; 443 status = "disabled"; 444 }; 445 446 pwm1: pwm@110b0010 { 447 compatible = "rockchip,rk3288-pwm"; 448 reg = <0x110b0010 0x10>; 449 #pwm-cells = <3>; 450 clocks = <&cru PCLK_PWM>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pwm1_pin>; 453 status = "disabled"; 454 }; 455 456 pwm2: pwm@110b0020 { 457 compatible = "rockchip,rk3288-pwm"; 458 reg = <0x110b0020 0x10>; 459 #pwm-cells = <3>; 460 clocks = <&cru PCLK_PWM>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pwm2_pin>; 463 status = "disabled"; 464 }; 465 466 pwm3: pwm@110b0030 { 467 compatible = "rockchip,rk3288-pwm"; 468 reg = <0x110b0030 0x10>; 469 #pwm-cells = <2>; 470 clocks = <&cru PCLK_PWM>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pwm3_pin>; 473 status = "disabled"; 474 }; 475 476 timer: timer@110c0000 { 477 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; 478 reg = <0x110c0000 0x20>; 479 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cru PCLK_TIMER>, <&xin24m>; 481 clock-names = "pclk", "timer"; 482 }; 483 484 cru: clock-controller@110e0000 { 485 compatible = "rockchip,rk3228-cru"; 486 reg = <0x110e0000 0x1000>; 487 rockchip,grf = <&grf>; 488 #clock-cells = <1>; 489 #reset-cells = <1>; 490 assigned-clocks = 491 <&cru PLL_GPLL>, <&cru ARMCLK>, 492 <&cru PLL_CPLL>, <&cru ACLK_PERI>, 493 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 494 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 495 <&cru PCLK_CPU>; 496 assigned-clock-rates = 497 <594000000>, <816000000>, 498 <500000000>, <150000000>, 499 <150000000>, <75000000>, 500 <150000000>, <150000000>, 501 <75000000>; 502 }; 503 504 pdma: pdma@110f0000 { 505 compatible = "arm,pl330", "arm,primecell"; 506 reg = <0x110f0000 0x4000>; 507 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 509 #dma-cells = <1>; 510 arm,pl330-periph-burst; 511 clocks = <&cru ACLK_DMAC>; 512 clock-names = "apb_pclk"; 513 }; 514 515 thermal-zones { 516 cpu_thermal: cpu-thermal { 517 polling-delay-passive = <100>; /* milliseconds */ 518 polling-delay = <5000>; /* milliseconds */ 519 520 thermal-sensors = <&tsadc 0>; 521 522 trips { 523 cpu_alert0: cpu_alert0 { 524 temperature = <70000>; /* millicelsius */ 525 hysteresis = <2000>; /* millicelsius */ 526 type = "passive"; 527 }; 528 cpu_alert1: cpu_alert1 { 529 temperature = <75000>; /* millicelsius */ 530 hysteresis = <2000>; /* millicelsius */ 531 type = "passive"; 532 }; 533 cpu_crit: cpu_crit { 534 temperature = <90000>; /* millicelsius */ 535 hysteresis = <2000>; /* millicelsius */ 536 type = "critical"; 537 }; 538 }; 539 540 cooling-maps { 541 map0 { 542 trip = <&cpu_alert0>; 543 cooling-device = 544 <&cpu0 THERMAL_NO_LIMIT 6>, 545 <&cpu1 THERMAL_NO_LIMIT 6>, 546 <&cpu2 THERMAL_NO_LIMIT 6>, 547 <&cpu3 THERMAL_NO_LIMIT 6>; 548 }; 549 map1 { 550 trip = <&cpu_alert1>; 551 cooling-device = 552 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 553 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 554 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 555 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 556 }; 557 }; 558 }; 559 }; 560 561 tsadc: tsadc@11150000 { 562 compatible = "rockchip,rk3228-tsadc"; 563 reg = <0x11150000 0x100>; 564 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 566 clock-names = "tsadc", "apb_pclk"; 567 assigned-clocks = <&cru SCLK_TSADC>; 568 assigned-clock-rates = <32768>; 569 resets = <&cru SRST_TSADC>; 570 reset-names = "tsadc-apb"; 571 pinctrl-names = "init", "default", "sleep"; 572 pinctrl-0 = <&otp_pin>; 573 pinctrl-1 = <&otp_out>; 574 pinctrl-2 = <&otp_pin>; 575 #thermal-sensor-cells = <1>; 576 rockchip,hw-tshut-temp = <95000>; 577 status = "disabled"; 578 }; 579 580 hdmi_phy: hdmi-phy@12030000 { 581 compatible = "rockchip,rk3228-hdmi-phy"; 582 reg = <0x12030000 0x10000>; 583 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; 584 clock-names = "sysclk", "refoclk", "refpclk"; 585 #clock-cells = <0>; 586 clock-output-names = "hdmiphy_phy"; 587 #phy-cells = <0>; 588 status = "disabled"; 589 }; 590 591 gpu: gpu@20000000 { 592 compatible = "rockchip,rk3228-mali", "arm,mali-400"; 593 reg = <0x20000000 0x10000>; 594 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 600 interrupt-names = "gp", 601 "gpmmu", 602 "pp0", 603 "ppmmu0", 604 "pp1", 605 "ppmmu1"; 606 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 607 clock-names = "bus", "core"; 608 power-domains = <&power RK3228_PD_GPU>; 609 resets = <&cru SRST_GPU_A>; 610 status = "disabled"; 611 }; 612 613 vpu: video-codec@20020000 { 614 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; 615 reg = <0x20020000 0x800>; 616 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-names = "vepu", "vdpu"; 619 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 620 clock-names = "aclk", "hclk"; 621 iommus = <&vpu_mmu>; 622 power-domains = <&power RK3228_PD_VPU>; 623 }; 624 625 vpu_mmu: iommu@20020800 { 626 compatible = "rockchip,iommu"; 627 reg = <0x20020800 0x100>; 628 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 630 clock-names = "aclk", "iface"; 631 power-domains = <&power RK3228_PD_VPU>; 632 #iommu-cells = <0>; 633 }; 634 635 vdec: video-codec@20030000 { 636 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; 637 reg = <0x20030000 0x480>; 638 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 640 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 641 clock-names = "axi", "ahb", "cabac", "core"; 642 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 643 assigned-clock-rates = <300000000>, <300000000>; 644 iommus = <&vdec_mmu>; 645 power-domains = <&power RK3228_PD_RKVDEC>; 646 }; 647 648 vdec_mmu: iommu@20030480 { 649 compatible = "rockchip,iommu"; 650 reg = <0x20030480 0x40>, <0x200304c0 0x40>; 651 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 653 clock-names = "aclk", "iface"; 654 power-domains = <&power RK3228_PD_RKVDEC>; 655 #iommu-cells = <0>; 656 }; 657 658 vop: vop@20050000 { 659 compatible = "rockchip,rk3228-vop"; 660 reg = <0x20050000 0x1ffc>; 661 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 663 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 664 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 665 reset-names = "axi", "ahb", "dclk"; 666 iommus = <&vop_mmu>; 667 power-domains = <&power RK3228_PD_VOP>; 668 status = "disabled"; 669 670 vop_out: port { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 674 vop_out_hdmi: endpoint@0 { 675 reg = <0>; 676 remote-endpoint = <&hdmi_in_vop>; 677 }; 678 }; 679 }; 680 681 vop_mmu: iommu@20053f00 { 682 compatible = "rockchip,iommu"; 683 reg = <0x20053f00 0x100>; 684 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 686 clock-names = "aclk", "iface"; 687 power-domains = <&power RK3228_PD_VOP>; 688 #iommu-cells = <0>; 689 status = "disabled"; 690 }; 691 692 rga: rga@20060000 { 693 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; 694 reg = <0x20060000 0x1000>; 695 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 697 clock-names = "aclk", "hclk", "sclk"; 698 power-domains = <&power RK3228_PD_VIO>; 699 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; 700 reset-names = "core", "axi", "ahb"; 701 }; 702 703 iep_mmu: iommu@20070800 { 704 compatible = "rockchip,iommu"; 705 reg = <0x20070800 0x100>; 706 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 708 clock-names = "aclk", "iface"; 709 power-domains = <&power RK3228_PD_VIO>; 710 #iommu-cells = <0>; 711 status = "disabled"; 712 }; 713 714 hdmi: hdmi@200a0000 { 715 compatible = "rockchip,rk3228-dw-hdmi"; 716 reg = <0x200a0000 0x20000>; 717 reg-io-width = <4>; 718 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 719 assigned-clocks = <&cru SCLK_HDMI_PHY>; 720 assigned-clock-parents = <&hdmi_phy>; 721 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; 722 clock-names = "isfr", "iahb", "cec"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 725 resets = <&cru SRST_HDMI_P>; 726 reset-names = "hdmi"; 727 phys = <&hdmi_phy>; 728 phy-names = "hdmi"; 729 rockchip,grf = <&grf>; 730 status = "disabled"; 731 732 ports { 733 hdmi_in: port { 734 #address-cells = <1>; 735 #size-cells = <0>; 736 hdmi_in_vop: endpoint@0 { 737 reg = <0>; 738 remote-endpoint = <&vop_out_hdmi>; 739 }; 740 }; 741 }; 742 }; 743 744 sdmmc: mmc@30000000 { 745 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 746 reg = <0x30000000 0x4000>; 747 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 749 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 750 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 751 fifo-depth = <0x100>; 752 pinctrl-names = "default"; 753 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 754 status = "disabled"; 755 }; 756 757 sdio: mmc@30010000 { 758 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 759 reg = <0x30010000 0x4000>; 760 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 762 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 763 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 764 fifo-depth = <0x100>; 765 pinctrl-names = "default"; 766 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 767 status = "disabled"; 768 }; 769 770 emmc: mmc@30020000 { 771 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 772 reg = <0x30020000 0x4000>; 773 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 774 clock-frequency = <37500000>; 775 max-frequency = <37500000>; 776 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 777 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 778 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 779 bus-width = <8>; 780 rockchip,default-sample-phase = <158>; 781 fifo-depth = <0x100>; 782 pinctrl-names = "default"; 783 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 784 resets = <&cru SRST_EMMC>; 785 reset-names = "reset"; 786 status = "disabled"; 787 }; 788 789 usb_otg: usb@30040000 { 790 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", 791 "snps,dwc2"; 792 reg = <0x30040000 0x40000>; 793 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&cru HCLK_OTG>; 795 clock-names = "otg"; 796 dr_mode = "otg"; 797 g-np-tx-fifo-size = <16>; 798 g-rx-fifo-size = <280>; 799 g-tx-fifo-size = <256 128 128 64 32 16>; 800 phys = <&u2phy0_otg>; 801 phy-names = "usb2-phy"; 802 status = "disabled"; 803 }; 804 805 usb_host0_ehci: usb@30080000 { 806 compatible = "generic-ehci"; 807 reg = <0x30080000 0x20000>; 808 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 810 phys = <&u2phy0_host>; 811 phy-names = "usb"; 812 status = "disabled"; 813 }; 814 815 usb_host0_ohci: usb@300a0000 { 816 compatible = "generic-ohci"; 817 reg = <0x300a0000 0x20000>; 818 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 820 phys = <&u2phy0_host>; 821 phy-names = "usb"; 822 status = "disabled"; 823 }; 824 825 usb_host1_ehci: usb@300c0000 { 826 compatible = "generic-ehci"; 827 reg = <0x300c0000 0x20000>; 828 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 830 phys = <&u2phy1_otg>; 831 phy-names = "usb"; 832 status = "disabled"; 833 }; 834 835 usb_host1_ohci: usb@300e0000 { 836 compatible = "generic-ohci"; 837 reg = <0x300e0000 0x20000>; 838 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 840 phys = <&u2phy1_otg>; 841 phy-names = "usb"; 842 status = "disabled"; 843 }; 844 845 usb_host2_ehci: usb@30100000 { 846 compatible = "generic-ehci"; 847 reg = <0x30100000 0x20000>; 848 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 850 phys = <&u2phy1_host>; 851 phy-names = "usb"; 852 status = "disabled"; 853 }; 854 855 usb_host2_ohci: usb@30120000 { 856 compatible = "generic-ohci"; 857 reg = <0x30120000 0x20000>; 858 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 860 phys = <&u2phy1_host>; 861 phy-names = "usb"; 862 status = "disabled"; 863 }; 864 865 gmac: ethernet@30200000 { 866 compatible = "rockchip,rk3228-gmac"; 867 reg = <0x30200000 0x10000>; 868 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 869 interrupt-names = "macirq"; 870 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 871 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 872 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 873 <&cru PCLK_GMAC>; 874 clock-names = "stmmaceth", "mac_clk_rx", 875 "mac_clk_tx", "clk_mac_ref", 876 "clk_mac_refout", "aclk_mac", 877 "pclk_mac"; 878 resets = <&cru SRST_GMAC>; 879 reset-names = "stmmaceth"; 880 rockchip,grf = <&grf>; 881 status = "disabled"; 882 }; 883 884 qos_iep: qos@31030080 { 885 compatible = "rockchip,rk3228-qos", "syscon"; 886 reg = <0x31030080 0x20>; 887 }; 888 889 qos_rga_w: qos@31030100 { 890 compatible = "rockchip,rk3228-qos", "syscon"; 891 reg = <0x31030100 0x20>; 892 }; 893 894 qos_hdcp: qos@31030180 { 895 compatible = "rockchip,rk3228-qos", "syscon"; 896 reg = <0x31030180 0x20>; 897 }; 898 899 qos_rga_r: qos@31030200 { 900 compatible = "rockchip,rk3228-qos", "syscon"; 901 reg = <0x31030200 0x20>; 902 }; 903 904 qos_vpu: qos@31040000 { 905 compatible = "rockchip,rk3228-qos", "syscon"; 906 reg = <0x31040000 0x20>; 907 }; 908 909 qos_gpu: qos@31050000 { 910 compatible = "rockchip,rk3228-qos", "syscon"; 911 reg = <0x31050000 0x20>; 912 }; 913 914 qos_vop: qos@31060000 { 915 compatible = "rockchip,rk3228-qos", "syscon"; 916 reg = <0x31060000 0x20>; 917 }; 918 919 qos_rkvdec_r: qos@31070000 { 920 compatible = "rockchip,rk3228-qos", "syscon"; 921 reg = <0x31070000 0x20>; 922 }; 923 924 qos_rkvdec_w: qos@31070080 { 925 compatible = "rockchip,rk3228-qos", "syscon"; 926 reg = <0x31070080 0x20>; 927 }; 928 929 gic: interrupt-controller@32010000 { 930 compatible = "arm,gic-400"; 931 interrupt-controller; 932 #interrupt-cells = <3>; 933 #address-cells = <0>; 934 935 reg = <0x32011000 0x1000>, 936 <0x32012000 0x2000>, 937 <0x32014000 0x2000>, 938 <0x32016000 0x2000>; 939 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 940 }; 941 942 pinctrl: pinctrl { 943 compatible = "rockchip,rk3228-pinctrl"; 944 rockchip,grf = <&grf>; 945 #address-cells = <1>; 946 #size-cells = <1>; 947 ranges; 948 949 gpio0: gpio@11110000 { 950 compatible = "rockchip,gpio-bank"; 951 reg = <0x11110000 0x100>; 952 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&cru PCLK_GPIO0>; 954 955 gpio-controller; 956 #gpio-cells = <2>; 957 958 interrupt-controller; 959 #interrupt-cells = <2>; 960 }; 961 962 gpio1: gpio@11120000 { 963 compatible = "rockchip,gpio-bank"; 964 reg = <0x11120000 0x100>; 965 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&cru PCLK_GPIO1>; 967 968 gpio-controller; 969 #gpio-cells = <2>; 970 971 interrupt-controller; 972 #interrupt-cells = <2>; 973 }; 974 975 gpio2: gpio@11130000 { 976 compatible = "rockchip,gpio-bank"; 977 reg = <0x11130000 0x100>; 978 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&cru PCLK_GPIO2>; 980 981 gpio-controller; 982 #gpio-cells = <2>; 983 984 interrupt-controller; 985 #interrupt-cells = <2>; 986 }; 987 988 gpio3: gpio@11140000 { 989 compatible = "rockchip,gpio-bank"; 990 reg = <0x11140000 0x100>; 991 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&cru PCLK_GPIO3>; 993 994 gpio-controller; 995 #gpio-cells = <2>; 996 997 interrupt-controller; 998 #interrupt-cells = <2>; 999 }; 1000 1001 pcfg_pull_up: pcfg-pull-up { 1002 bias-pull-up; 1003 }; 1004 1005 pcfg_pull_down: pcfg-pull-down { 1006 bias-pull-down; 1007 }; 1008 1009 pcfg_pull_none: pcfg-pull-none { 1010 bias-disable; 1011 }; 1012 1013 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 1014 drive-strength = <12>; 1015 }; 1016 1017 sdmmc { 1018 sdmmc_clk: sdmmc-clk { 1019 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; 1020 }; 1021 1022 sdmmc_cmd: sdmmc-cmd { 1023 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; 1024 }; 1025 1026 sdmmc_bus4: sdmmc-bus4 { 1027 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 1028 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 1029 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, 1030 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; 1031 }; 1032 }; 1033 1034 sdio { 1035 sdio_clk: sdio-clk { 1036 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; 1037 }; 1038 1039 sdio_cmd: sdio-cmd { 1040 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; 1041 }; 1042 1043 sdio_bus4: sdio-bus4 { 1044 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, 1045 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, 1046 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, 1047 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; 1048 }; 1049 }; 1050 1051 emmc { 1052 emmc_clk: emmc-clk { 1053 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 1054 }; 1055 1056 emmc_cmd: emmc-cmd { 1057 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; 1058 }; 1059 1060 emmc_bus8: emmc-bus8 { 1061 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, 1062 <1 RK_PD1 2 &pcfg_pull_none>, 1063 <1 RK_PD2 2 &pcfg_pull_none>, 1064 <1 RK_PD3 2 &pcfg_pull_none>, 1065 <1 RK_PD4 2 &pcfg_pull_none>, 1066 <1 RK_PD5 2 &pcfg_pull_none>, 1067 <1 RK_PD6 2 &pcfg_pull_none>, 1068 <1 RK_PD7 2 &pcfg_pull_none>; 1069 }; 1070 }; 1071 1072 gmac { 1073 rgmii_pins: rgmii-pins { 1074 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 1075 <2 RK_PB4 1 &pcfg_pull_none>, 1076 <2 RK_PD1 1 &pcfg_pull_none>, 1077 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 1078 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 1079 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, 1080 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, 1081 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, 1082 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 1083 <2 RK_PC1 1 &pcfg_pull_none>, 1084 <2 RK_PC0 1 &pcfg_pull_none>, 1085 <2 RK_PC5 2 &pcfg_pull_none>, 1086 <2 RK_PC4 2 &pcfg_pull_none>, 1087 <2 RK_PB3 1 &pcfg_pull_none>, 1088 <2 RK_PB0 1 &pcfg_pull_none>; 1089 }; 1090 1091 rmii_pins: rmii-pins { 1092 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 1093 <2 RK_PB4 1 &pcfg_pull_none>, 1094 <2 RK_PD1 1 &pcfg_pull_none>, 1095 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 1096 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 1097 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 1098 <2 RK_PC1 1 &pcfg_pull_none>, 1099 <2 RK_PC0 1 &pcfg_pull_none>, 1100 <2 RK_PB0 1 &pcfg_pull_none>, 1101 <2 RK_PB7 1 &pcfg_pull_none>; 1102 }; 1103 1104 phy_pins: phy-pins { 1105 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, 1106 <2 RK_PB0 2 &pcfg_pull_none>; 1107 }; 1108 }; 1109 1110 hdmi { 1111 hdmi_hpd: hdmi-hpd { 1112 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; 1113 }; 1114 1115 hdmii2c_xfer: hdmii2c-xfer { 1116 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 1117 <0 RK_PA7 2 &pcfg_pull_none>; 1118 }; 1119 1120 hdmi_cec: hdmi-cec { 1121 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 1122 }; 1123 }; 1124 1125 i2c0 { 1126 i2c0_xfer: i2c0-xfer { 1127 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 1128 <0 RK_PA1 1 &pcfg_pull_none>; 1129 }; 1130 }; 1131 1132 i2c1 { 1133 i2c1_xfer: i2c1-xfer { 1134 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 1135 <0 RK_PA3 1 &pcfg_pull_none>; 1136 }; 1137 }; 1138 1139 i2c2 { 1140 i2c2_xfer: i2c2-xfer { 1141 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 1142 <2 RK_PC5 1 &pcfg_pull_none>; 1143 }; 1144 }; 1145 1146 i2c3 { 1147 i2c3_xfer: i2c3-xfer { 1148 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1149 <0 RK_PA7 1 &pcfg_pull_none>; 1150 }; 1151 }; 1152 1153 spi0 { 1154 spi0_clk: spi0-clk { 1155 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; 1156 }; 1157 spi0_cs0: spi0-cs0 { 1158 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; 1159 }; 1160 spi0_tx: spi0-tx { 1161 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; 1162 }; 1163 spi0_rx: spi0-rx { 1164 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; 1165 }; 1166 spi0_cs1: spi0-cs1 { 1167 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; 1168 }; 1169 }; 1170 1171 spi1 { 1172 spi1_clk: spi1-clk { 1173 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; 1174 }; 1175 spi1_cs0: spi1-cs0 { 1176 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; 1177 }; 1178 spi1_rx: spi1-rx { 1179 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; 1180 }; 1181 spi1_tx: spi1-tx { 1182 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; 1183 }; 1184 spi1_cs1: spi1-cs1 { 1185 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; 1186 }; 1187 }; 1188 1189 i2s1 { 1190 i2s1_bus: i2s1-bus { 1191 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 1192 <0 RK_PB1 1 &pcfg_pull_none>, 1193 <0 RK_PB3 1 &pcfg_pull_none>, 1194 <0 RK_PB4 1 &pcfg_pull_none>, 1195 <0 RK_PB5 1 &pcfg_pull_none>, 1196 <0 RK_PB6 1 &pcfg_pull_none>, 1197 <1 RK_PA2 2 &pcfg_pull_none>, 1198 <1 RK_PA4 2 &pcfg_pull_none>, 1199 <1 RK_PA5 2 &pcfg_pull_none>; 1200 }; 1201 }; 1202 1203 pwm0 { 1204 pwm0_pin: pwm0-pin { 1205 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 1206 }; 1207 }; 1208 1209 pwm1 { 1210 pwm1_pin: pwm1-pin { 1211 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1212 }; 1213 }; 1214 1215 pwm2 { 1216 pwm2_pin: pwm2-pin { 1217 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; 1218 }; 1219 }; 1220 1221 pwm3 { 1222 pwm3_pin: pwm3-pin { 1223 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1224 }; 1225 }; 1226 1227 spdif { 1228 spdif_tx: spdif-tx { 1229 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; 1230 }; 1231 }; 1232 1233 tsadc { 1234 otp_pin: otp-pin { 1235 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 1236 }; 1237 1238 otp_out: otp-out { 1239 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 1240 }; 1241 }; 1242 1243 uart0 { 1244 uart0_xfer: uart0-xfer { 1245 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, 1246 <2 RK_PD3 1 &pcfg_pull_none>; 1247 }; 1248 1249 uart0_cts: uart0-cts { 1250 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; 1251 }; 1252 1253 uart0_rts: uart0-rts { 1254 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; 1255 }; 1256 }; 1257 1258 uart1 { 1259 uart1_xfer: uart1-xfer { 1260 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1261 <1 RK_PB2 1 &pcfg_pull_none>; 1262 }; 1263 1264 uart1_cts: uart1-cts { 1265 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; 1266 }; 1267 1268 uart1_rts: uart1-rts { 1269 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1270 }; 1271 }; 1272 1273 uart2 { 1274 uart2_xfer: uart2-xfer { 1275 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 1276 <1 RK_PC3 2 &pcfg_pull_none>; 1277 }; 1278 1279 uart21_xfer: uart21-xfer { 1280 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, 1281 <1 RK_PB1 2 &pcfg_pull_none>; 1282 }; 1283 1284 uart2_cts: uart2-cts { 1285 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1286 }; 1287 1288 uart2_rts: uart2-rts { 1289 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1290 }; 1291 }; 1292 }; 1293}; 1294