1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/thermal/thermal.h> 47 48#include <dt-bindings/clock/sun6i-a31-ccu.h> 49#include <dt-bindings/reset/sun6i-a31-ccu.h> 50 51/ { 52 interrupt-parent = <&gic>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 aliases { 57 ethernet0 = &gmac; 58 }; 59 60 chosen { 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges; 64 65 simplefb_hdmi: framebuffer-lcd0-hdmi { 66 compatible = "allwinner,simple-framebuffer", 67 "simple-framebuffer"; 68 allwinner,pipeline = "de_be0-lcd0-hdmi"; 69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, 70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, 71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, 72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; 73 status = "disabled"; 74 }; 75 76 simplefb_lcd: framebuffer-lcd0 { 77 compatible = "allwinner,simple-framebuffer", 78 "simple-framebuffer"; 79 allwinner,pipeline = "de_be0-lcd0"; 80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, 81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, 82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; 83 status = "disabled"; 84 }; 85 }; 86 87 timer { 88 compatible = "arm,armv7-timer"; 89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 93 clock-frequency = <24000000>; 94 arm,cpu-registers-not-fw-configured; 95 }; 96 97 cpus { 98 enable-method = "allwinner,sun6i-a31"; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 cpu0: cpu@0 { 103 compatible = "arm,cortex-a7"; 104 device_type = "cpu"; 105 reg = <0>; 106 clocks = <&ccu CLK_CPU>; 107 clock-latency = <244144>; /* 8 32k periods */ 108 operating-points = 109 /* kHz uV */ 110 <1008000 1200000>, 111 <864000 1200000>, 112 <720000 1100000>, 113 <480000 1000000>; 114 #cooling-cells = <2>; 115 }; 116 117 cpu1: cpu@1 { 118 compatible = "arm,cortex-a7"; 119 device_type = "cpu"; 120 reg = <1>; 121 clocks = <&ccu CLK_CPU>; 122 clock-latency = <244144>; /* 8 32k periods */ 123 operating-points = 124 /* kHz uV */ 125 <1008000 1200000>, 126 <864000 1200000>, 127 <720000 1100000>, 128 <480000 1000000>; 129 #cooling-cells = <2>; 130 }; 131 132 cpu2: cpu@2 { 133 compatible = "arm,cortex-a7"; 134 device_type = "cpu"; 135 reg = <2>; 136 clocks = <&ccu CLK_CPU>; 137 clock-latency = <244144>; /* 8 32k periods */ 138 operating-points = 139 /* kHz uV */ 140 <1008000 1200000>, 141 <864000 1200000>, 142 <720000 1100000>, 143 <480000 1000000>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu3: cpu@3 { 148 compatible = "arm,cortex-a7"; 149 device_type = "cpu"; 150 reg = <3>; 151 clocks = <&ccu CLK_CPU>; 152 clock-latency = <244144>; /* 8 32k periods */ 153 operating-points = 154 /* kHz uV */ 155 <1008000 1200000>, 156 <864000 1200000>, 157 <720000 1100000>, 158 <480000 1000000>; 159 #cooling-cells = <2>; 160 }; 161 }; 162 163 thermal-zones { 164 cpu-thermal { 165 /* milliseconds */ 166 polling-delay-passive = <250>; 167 polling-delay = <1000>; 168 thermal-sensors = <&rtp>; 169 170 cooling-maps { 171 map0 { 172 trip = <&cpu_alert0>; 173 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 174 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 175 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 176 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 177 }; 178 }; 179 180 trips { 181 cpu_alert0: cpu_alert0 { 182 /* milliCelsius */ 183 temperature = <70000>; 184 hysteresis = <2000>; 185 type = "passive"; 186 }; 187 188 cpu_crit: cpu_crit { 189 /* milliCelsius */ 190 temperature = <100000>; 191 hysteresis = <2000>; 192 type = "critical"; 193 }; 194 }; 195 }; 196 }; 197 198 pmu { 199 compatible = "arm,cortex-a7-pmu"; 200 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 204 }; 205 206 clocks { 207 #address-cells = <1>; 208 #size-cells = <1>; 209 ranges; 210 211 osc24M: clk-24M { 212 #clock-cells = <0>; 213 compatible = "fixed-clock"; 214 clock-frequency = <24000000>; 215 clock-accuracy = <50000>; 216 clock-output-names = "osc24M"; 217 }; 218 219 osc32k: clk-32k { 220 #clock-cells = <0>; 221 compatible = "fixed-clock"; 222 clock-frequency = <32768>; 223 clock-accuracy = <50000>; 224 clock-output-names = "ext_osc32k"; 225 }; 226 227 /* 228 * The following two are dummy clocks, placeholders 229 * used in the gmac_tx clock. The gmac driver will 230 * choose one parent depending on the PHY interface 231 * mode, using clk_set_rate auto-reparenting. 232 * 233 * The actual TX clock rate is not controlled by the 234 * gmac_tx clock. 235 */ 236 mii_phy_tx_clk: clk-mii-phy-tx { 237 #clock-cells = <0>; 238 compatible = "fixed-clock"; 239 clock-frequency = <25000000>; 240 clock-output-names = "mii_phy_tx"; 241 }; 242 243 gmac_int_tx_clk: clk-gmac-int-tx { 244 #clock-cells = <0>; 245 compatible = "fixed-clock"; 246 clock-frequency = <125000000>; 247 clock-output-names = "gmac_int_tx"; 248 }; 249 250 gmac_tx_clk: clk@1c200d0 { 251 #clock-cells = <0>; 252 compatible = "allwinner,sun7i-a20-gmac-clk"; 253 reg = <0x01c200d0 0x4>; 254 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 255 clock-output-names = "gmac_tx"; 256 }; 257 }; 258 259 de: display-engine { 260 compatible = "allwinner,sun6i-a31-display-engine"; 261 allwinner,pipelines = <&fe0>, <&fe1>; 262 status = "disabled"; 263 }; 264 265 soc { 266 compatible = "simple-bus"; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 ranges; 270 271 dma: dma-controller@1c02000 { 272 compatible = "allwinner,sun6i-a31-dma"; 273 reg = <0x01c02000 0x1000>; 274 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&ccu CLK_AHB1_DMA>; 276 resets = <&ccu RST_AHB1_DMA>; 277 #dma-cells = <1>; 278 }; 279 280 tcon0: lcd-controller@1c0c000 { 281 compatible = "allwinner,sun6i-a31-tcon"; 282 reg = <0x01c0c000 0x1000>; 283 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 284 dmas = <&dma 11>; 285 resets = <&ccu RST_AHB1_LCD0>, 286 <&ccu RST_AHB1_LVDS>; 287 reset-names = "lcd", 288 "lvds"; 289 clocks = <&ccu CLK_AHB1_LCD0>, 290 <&ccu CLK_LCD0_CH0>, 291 <&ccu CLK_LCD0_CH1>, 292 <&ccu 15>; 293 clock-names = "ahb", 294 "tcon-ch0", 295 "tcon-ch1", 296 "lvds-alt"; 297 clock-output-names = "tcon0-pixel-clock"; 298 #clock-cells = <0>; 299 300 ports { 301 #address-cells = <1>; 302 #size-cells = <0>; 303 304 tcon0_in: port@0 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 reg = <0>; 308 309 tcon0_in_drc0: endpoint@0 { 310 reg = <0>; 311 remote-endpoint = <&drc0_out_tcon0>; 312 }; 313 314 tcon0_in_drc1: endpoint@1 { 315 reg = <1>; 316 remote-endpoint = <&drc1_out_tcon0>; 317 }; 318 }; 319 320 tcon0_out: port@1 { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 reg = <1>; 324 325 tcon0_out_hdmi: endpoint@1 { 326 reg = <1>; 327 remote-endpoint = <&hdmi_in_tcon0>; 328 allwinner,tcon-channel = <1>; 329 }; 330 }; 331 }; 332 }; 333 334 tcon1: lcd-controller@1c0d000 { 335 compatible = "allwinner,sun6i-a31-tcon"; 336 reg = <0x01c0d000 0x1000>; 337 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 338 dmas = <&dma 12>; 339 resets = <&ccu RST_AHB1_LCD1>, 340 <&ccu RST_AHB1_LVDS>; 341 reset-names = "lcd", "lvds"; 342 clocks = <&ccu CLK_AHB1_LCD1>, 343 <&ccu CLK_LCD1_CH0>, 344 <&ccu CLK_LCD1_CH1>, 345 <&ccu 15>; 346 clock-names = "ahb", 347 "tcon-ch0", 348 "tcon-ch1", 349 "lvds-alt"; 350 clock-output-names = "tcon1-pixel-clock"; 351 #clock-cells = <0>; 352 353 ports { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 357 tcon1_in: port@0 { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 reg = <0>; 361 362 tcon1_in_drc0: endpoint@0 { 363 reg = <0>; 364 remote-endpoint = <&drc0_out_tcon1>; 365 }; 366 367 tcon1_in_drc1: endpoint@1 { 368 reg = <1>; 369 remote-endpoint = <&drc1_out_tcon1>; 370 }; 371 }; 372 373 tcon1_out: port@1 { 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <1>; 377 378 tcon1_out_hdmi: endpoint@1 { 379 reg = <1>; 380 remote-endpoint = <&hdmi_in_tcon1>; 381 allwinner,tcon-channel = <1>; 382 }; 383 }; 384 }; 385 }; 386 387 mmc0: mmc@1c0f000 { 388 compatible = "allwinner,sun7i-a20-mmc"; 389 reg = <0x01c0f000 0x1000>; 390 clocks = <&ccu CLK_AHB1_MMC0>, 391 <&ccu CLK_MMC0>, 392 <&ccu CLK_MMC0_OUTPUT>, 393 <&ccu CLK_MMC0_SAMPLE>; 394 clock-names = "ahb", 395 "mmc", 396 "output", 397 "sample"; 398 resets = <&ccu RST_AHB1_MMC0>; 399 reset-names = "ahb"; 400 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&mmc0_pins>; 403 status = "disabled"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 }; 407 408 mmc1: mmc@1c10000 { 409 compatible = "allwinner,sun7i-a20-mmc"; 410 reg = <0x01c10000 0x1000>; 411 clocks = <&ccu CLK_AHB1_MMC1>, 412 <&ccu CLK_MMC1>, 413 <&ccu CLK_MMC1_OUTPUT>, 414 <&ccu CLK_MMC1_SAMPLE>; 415 clock-names = "ahb", 416 "mmc", 417 "output", 418 "sample"; 419 resets = <&ccu RST_AHB1_MMC1>; 420 reset-names = "ahb"; 421 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&mmc1_pins>; 424 status = "disabled"; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 }; 428 429 mmc2: mmc@1c11000 { 430 compatible = "allwinner,sun7i-a20-mmc"; 431 reg = <0x01c11000 0x1000>; 432 clocks = <&ccu CLK_AHB1_MMC2>, 433 <&ccu CLK_MMC2>, 434 <&ccu CLK_MMC2_OUTPUT>, 435 <&ccu CLK_MMC2_SAMPLE>; 436 clock-names = "ahb", 437 "mmc", 438 "output", 439 "sample"; 440 resets = <&ccu RST_AHB1_MMC2>; 441 reset-names = "ahb"; 442 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 443 status = "disabled"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 448 mmc3: mmc@1c12000 { 449 compatible = "allwinner,sun7i-a20-mmc"; 450 reg = <0x01c12000 0x1000>; 451 clocks = <&ccu CLK_AHB1_MMC3>, 452 <&ccu CLK_MMC3>, 453 <&ccu CLK_MMC3_OUTPUT>, 454 <&ccu CLK_MMC3_SAMPLE>; 455 clock-names = "ahb", 456 "mmc", 457 "output", 458 "sample"; 459 resets = <&ccu RST_AHB1_MMC3>; 460 reset-names = "ahb"; 461 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 462 status = "disabled"; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 }; 466 467 hdmi: hdmi@1c16000 { 468 compatible = "allwinner,sun6i-a31-hdmi"; 469 reg = <0x01c16000 0x1000>; 470 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, 472 <&ccu CLK_HDMI_DDC>, 473 <&ccu CLK_PLL_VIDEO0_2X>, 474 <&ccu CLK_PLL_VIDEO1_2X>; 475 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; 476 resets = <&ccu RST_AHB1_HDMI>; 477 dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 478 dmas = <&dma 13>, <&dma 13>, <&dma 14>; 479 status = "disabled"; 480 481 ports { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 485 hdmi_in: port@0 { 486 #address-cells = <1>; 487 #size-cells = <0>; 488 reg = <0>; 489 490 hdmi_in_tcon0: endpoint@0 { 491 reg = <0>; 492 remote-endpoint = <&tcon0_out_hdmi>; 493 }; 494 495 hdmi_in_tcon1: endpoint@1 { 496 reg = <1>; 497 remote-endpoint = <&tcon1_out_hdmi>; 498 }; 499 }; 500 501 hdmi_out: port@1 { 502 reg = <1>; 503 }; 504 }; 505 }; 506 507 usb_otg: usb@1c19000 { 508 compatible = "allwinner,sun6i-a31-musb"; 509 reg = <0x01c19000 0x0400>; 510 clocks = <&ccu CLK_AHB1_OTG>; 511 resets = <&ccu RST_AHB1_OTG>; 512 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "mc"; 514 phys = <&usbphy 0>; 515 phy-names = "usb"; 516 extcon = <&usbphy 0>; 517 dr_mode = "otg"; 518 status = "disabled"; 519 }; 520 521 usbphy: phy@1c19400 { 522 compatible = "allwinner,sun6i-a31-usb-phy"; 523 reg = <0x01c19400 0x10>, 524 <0x01c1a800 0x4>, 525 <0x01c1b800 0x4>; 526 reg-names = "phy_ctrl", 527 "pmu1", 528 "pmu2"; 529 clocks = <&ccu CLK_USB_PHY0>, 530 <&ccu CLK_USB_PHY1>, 531 <&ccu CLK_USB_PHY2>; 532 clock-names = "usb0_phy", 533 "usb1_phy", 534 "usb2_phy"; 535 resets = <&ccu RST_USB_PHY0>, 536 <&ccu RST_USB_PHY1>, 537 <&ccu RST_USB_PHY2>; 538 reset-names = "usb0_reset", 539 "usb1_reset", 540 "usb2_reset"; 541 status = "disabled"; 542 #phy-cells = <1>; 543 }; 544 545 ehci0: usb@1c1a000 { 546 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 547 reg = <0x01c1a000 0x100>; 548 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&ccu CLK_AHB1_EHCI0>; 550 resets = <&ccu RST_AHB1_EHCI0>; 551 phys = <&usbphy 1>; 552 phy-names = "usb"; 553 status = "disabled"; 554 }; 555 556 ohci0: usb@1c1a400 { 557 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 558 reg = <0x01c1a400 0x100>; 559 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; 561 resets = <&ccu RST_AHB1_OHCI0>; 562 phys = <&usbphy 1>; 563 phy-names = "usb"; 564 status = "disabled"; 565 }; 566 567 ehci1: usb@1c1b000 { 568 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 569 reg = <0x01c1b000 0x100>; 570 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&ccu CLK_AHB1_EHCI1>; 572 resets = <&ccu RST_AHB1_EHCI1>; 573 phys = <&usbphy 2>; 574 phy-names = "usb"; 575 status = "disabled"; 576 }; 577 578 ohci1: usb@1c1b400 { 579 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 580 reg = <0x01c1b400 0x100>; 581 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; 583 resets = <&ccu RST_AHB1_OHCI1>; 584 phys = <&usbphy 2>; 585 phy-names = "usb"; 586 status = "disabled"; 587 }; 588 589 ohci2: usb@1c1c400 { 590 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 591 reg = <0x01c1c400 0x100>; 592 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; 594 resets = <&ccu RST_AHB1_OHCI2>; 595 status = "disabled"; 596 }; 597 598 ccu: clock@1c20000 { 599 compatible = "allwinner,sun6i-a31-ccu"; 600 reg = <0x01c20000 0x400>; 601 clocks = <&osc24M>, <&rtc 0>; 602 clock-names = "hosc", "losc"; 603 #clock-cells = <1>; 604 #reset-cells = <1>; 605 }; 606 607 pio: pinctrl@1c20800 { 608 compatible = "allwinner,sun6i-a31-pinctrl"; 609 reg = <0x01c20800 0x400>; 610 interrupt-parent = <&r_intc>; 611 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; 616 clock-names = "apb", "hosc", "losc"; 617 gpio-controller; 618 interrupt-controller; 619 #interrupt-cells = <3>; 620 #gpio-cells = <3>; 621 622 gmac_gmii_pins: gmac-gmii-pins { 623 pins = "PA0", "PA1", "PA2", "PA3", 624 "PA4", "PA5", "PA6", "PA7", 625 "PA8", "PA9", "PA10", "PA11", 626 "PA12", "PA13", "PA14", "PA15", 627 "PA16", "PA17", "PA18", "PA19", 628 "PA20", "PA21", "PA22", "PA23", 629 "PA24", "PA25", "PA26", "PA27"; 630 function = "gmac"; 631 /* 632 * data lines in GMII mode run at 125MHz and 633 * might need a higher signal drive strength 634 */ 635 drive-strength = <30>; 636 }; 637 638 gmac_mii_pins: gmac-mii-pins { 639 pins = "PA0", "PA1", "PA2", "PA3", 640 "PA8", "PA9", "PA11", 641 "PA12", "PA13", "PA14", "PA19", 642 "PA20", "PA21", "PA22", "PA23", 643 "PA24", "PA26", "PA27"; 644 function = "gmac"; 645 }; 646 647 gmac_rgmii_pins: gmac-rgmii-pins { 648 pins = "PA0", "PA1", "PA2", "PA3", 649 "PA9", "PA10", "PA11", 650 "PA12", "PA13", "PA14", "PA19", 651 "PA20", "PA25", "PA26", "PA27"; 652 function = "gmac"; 653 /* 654 * data lines in RGMII mode use DDR mode 655 * and need a higher signal drive strength 656 */ 657 drive-strength = <40>; 658 }; 659 660 i2c0_pins: i2c0-pins { 661 pins = "PH14", "PH15"; 662 function = "i2c0"; 663 }; 664 665 i2c1_pins: i2c1-pins { 666 pins = "PH16", "PH17"; 667 function = "i2c1"; 668 }; 669 670 i2c2_pins: i2c2-pins { 671 pins = "PH18", "PH19"; 672 function = "i2c2"; 673 }; 674 675 lcd0_rgb888_pins: lcd0-rgb888-pins { 676 pins = "PD0", "PD1", "PD2", "PD3", 677 "PD4", "PD5", "PD6", "PD7", 678 "PD8", "PD9", "PD10", "PD11", 679 "PD12", "PD13", "PD14", "PD15", 680 "PD16", "PD17", "PD18", "PD19", 681 "PD20", "PD21", "PD22", "PD23", 682 "PD24", "PD25", "PD26", "PD27"; 683 function = "lcd0"; 684 }; 685 686 mmc0_pins: mmc0-pins { 687 pins = "PF0", "PF1", "PF2", 688 "PF3", "PF4", "PF5"; 689 function = "mmc0"; 690 drive-strength = <30>; 691 bias-pull-up; 692 }; 693 694 mmc1_pins: mmc1-pins { 695 pins = "PG0", "PG1", "PG2", "PG3", 696 "PG4", "PG5"; 697 function = "mmc1"; 698 drive-strength = <30>; 699 bias-pull-up; 700 }; 701 702 mmc2_4bit_pins: mmc2-4bit-pins { 703 pins = "PC6", "PC7", "PC8", "PC9", 704 "PC10", "PC11"; 705 function = "mmc2"; 706 drive-strength = <30>; 707 bias-pull-up; 708 }; 709 710 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { 711 pins = "PC6", "PC7", "PC8", "PC9", 712 "PC10", "PC11", "PC12", 713 "PC13", "PC14", "PC15", 714 "PC24"; 715 function = "mmc2"; 716 drive-strength = <30>; 717 bias-pull-up; 718 }; 719 720 mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins { 721 pins = "PC6", "PC7", "PC8", "PC9", 722 "PC10", "PC11", "PC12", 723 "PC13", "PC14", "PC15", 724 "PC24"; 725 function = "mmc3"; 726 drive-strength = <40>; 727 bias-pull-up; 728 }; 729 730 spdif_tx_pin: spdif-tx-pin { 731 pins = "PH28"; 732 function = "spdif"; 733 }; 734 735 uart0_ph_pins: uart0-ph-pins { 736 pins = "PH20", "PH21"; 737 function = "uart0"; 738 }; 739 }; 740 741 timer@1c20c00 { 742 compatible = "allwinner,sun4i-a10-timer"; 743 reg = <0x01c20c00 0xa0>; 744 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&osc24M>; 751 }; 752 753 wdt1: watchdog@1c20ca0 { 754 compatible = "allwinner,sun6i-a31-wdt"; 755 reg = <0x01c20ca0 0x20>; 756 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&osc24M>; 758 }; 759 760 spdif: spdif@1c21000 { 761 #sound-dai-cells = <0>; 762 compatible = "allwinner,sun6i-a31-spdif"; 763 reg = <0x01c21000 0x400>; 764 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>; 766 resets = <&ccu RST_APB1_SPDIF>; 767 clock-names = "apb", "spdif"; 768 dmas = <&dma 2>, <&dma 2>; 769 dma-names = "rx", "tx"; 770 status = "disabled"; 771 }; 772 773 i2s0: i2s@1c22000 { 774 #sound-dai-cells = <0>; 775 compatible = "allwinner,sun6i-a31-i2s"; 776 reg = <0x01c22000 0x400>; 777 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; 779 resets = <&ccu RST_APB1_DAUDIO0>; 780 clock-names = "apb", "mod"; 781 dmas = <&dma 3>, <&dma 3>; 782 dma-names = "rx", "tx"; 783 status = "disabled"; 784 }; 785 786 i2s1: i2s@1c22400 { 787 #sound-dai-cells = <0>; 788 compatible = "allwinner,sun6i-a31-i2s"; 789 reg = <0x01c22400 0x400>; 790 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; 792 resets = <&ccu RST_APB1_DAUDIO1>; 793 clock-names = "apb", "mod"; 794 dmas = <&dma 4>, <&dma 4>; 795 dma-names = "rx", "tx"; 796 status = "disabled"; 797 }; 798 799 lradc: lradc@1c22800 { 800 compatible = "allwinner,sun4i-a10-lradc-keys"; 801 reg = <0x01c22800 0x100>; 802 interrupt-parent = <&r_intc>; 803 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 804 status = "disabled"; 805 }; 806 807 rtp: rtp@1c25000 { 808 compatible = "allwinner,sun6i-a31-ts"; 809 reg = <0x01c25000 0x100>; 810 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 811 #thermal-sensor-cells = <0>; 812 }; 813 814 uart0: serial@1c28000 { 815 compatible = "snps,dw-apb-uart"; 816 reg = <0x01c28000 0x400>; 817 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 818 reg-shift = <2>; 819 reg-io-width = <4>; 820 clocks = <&ccu CLK_APB2_UART0>; 821 resets = <&ccu RST_APB2_UART0>; 822 dmas = <&dma 6>, <&dma 6>; 823 dma-names = "rx", "tx"; 824 status = "disabled"; 825 }; 826 827 uart1: serial@1c28400 { 828 compatible = "snps,dw-apb-uart"; 829 reg = <0x01c28400 0x400>; 830 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 831 reg-shift = <2>; 832 reg-io-width = <4>; 833 clocks = <&ccu CLK_APB2_UART1>; 834 resets = <&ccu RST_APB2_UART1>; 835 dmas = <&dma 7>, <&dma 7>; 836 dma-names = "rx", "tx"; 837 status = "disabled"; 838 }; 839 840 uart2: serial@1c28800 { 841 compatible = "snps,dw-apb-uart"; 842 reg = <0x01c28800 0x400>; 843 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 844 reg-shift = <2>; 845 reg-io-width = <4>; 846 clocks = <&ccu CLK_APB2_UART2>; 847 resets = <&ccu RST_APB2_UART2>; 848 dmas = <&dma 8>, <&dma 8>; 849 dma-names = "rx", "tx"; 850 status = "disabled"; 851 }; 852 853 uart3: serial@1c28c00 { 854 compatible = "snps,dw-apb-uart"; 855 reg = <0x01c28c00 0x400>; 856 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 857 reg-shift = <2>; 858 reg-io-width = <4>; 859 clocks = <&ccu CLK_APB2_UART3>; 860 resets = <&ccu RST_APB2_UART3>; 861 dmas = <&dma 9>, <&dma 9>; 862 dma-names = "rx", "tx"; 863 status = "disabled"; 864 }; 865 866 uart4: serial@1c29000 { 867 compatible = "snps,dw-apb-uart"; 868 reg = <0x01c29000 0x400>; 869 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 870 reg-shift = <2>; 871 reg-io-width = <4>; 872 clocks = <&ccu CLK_APB2_UART4>; 873 resets = <&ccu RST_APB2_UART4>; 874 dmas = <&dma 10>, <&dma 10>; 875 dma-names = "rx", "tx"; 876 status = "disabled"; 877 }; 878 879 uart5: serial@1c29400 { 880 compatible = "snps,dw-apb-uart"; 881 reg = <0x01c29400 0x400>; 882 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 883 reg-shift = <2>; 884 reg-io-width = <4>; 885 clocks = <&ccu CLK_APB2_UART5>; 886 resets = <&ccu RST_APB2_UART5>; 887 dmas = <&dma 22>, <&dma 22>; 888 dma-names = "rx", "tx"; 889 status = "disabled"; 890 }; 891 892 i2c0: i2c@1c2ac00 { 893 compatible = "allwinner,sun6i-a31-i2c"; 894 reg = <0x01c2ac00 0x400>; 895 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&ccu CLK_APB2_I2C0>; 897 resets = <&ccu RST_APB2_I2C0>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&i2c0_pins>; 900 status = "disabled"; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 }; 904 905 i2c1: i2c@1c2b000 { 906 compatible = "allwinner,sun6i-a31-i2c"; 907 reg = <0x01c2b000 0x400>; 908 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&ccu CLK_APB2_I2C1>; 910 resets = <&ccu RST_APB2_I2C1>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&i2c1_pins>; 913 status = "disabled"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 }; 917 918 i2c2: i2c@1c2b400 { 919 compatible = "allwinner,sun6i-a31-i2c"; 920 reg = <0x01c2b400 0x400>; 921 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&ccu CLK_APB2_I2C2>; 923 resets = <&ccu RST_APB2_I2C2>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&i2c2_pins>; 926 status = "disabled"; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 }; 930 931 i2c3: i2c@1c2b800 { 932 compatible = "allwinner,sun6i-a31-i2c"; 933 reg = <0x01c2b800 0x400>; 934 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&ccu CLK_APB2_I2C3>; 936 resets = <&ccu RST_APB2_I2C3>; 937 status = "disabled"; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 }; 941 942 gmac: ethernet@1c30000 { 943 compatible = "allwinner,sun7i-a20-gmac"; 944 reg = <0x01c30000 0x1054>; 945 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 946 interrupt-names = "macirq"; 947 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; 948 clock-names = "stmmaceth", "allwinner_gmac_tx"; 949 resets = <&ccu RST_AHB1_EMAC>; 950 reset-names = "stmmaceth"; 951 snps,pbl = <2>; 952 snps,fixed-burst; 953 snps,force_sf_dma_mode; 954 status = "disabled"; 955 956 mdio: mdio { 957 compatible = "snps,dwmac-mdio"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 }; 961 }; 962 963 crypto: crypto-engine@1c15000 { 964 compatible = "allwinner,sun6i-a31-crypto", 965 "allwinner,sun4i-a10-crypto"; 966 reg = <0x01c15000 0x1000>; 967 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; 969 clock-names = "ahb", "mod"; 970 resets = <&ccu RST_AHB1_SS>; 971 reset-names = "ahb"; 972 }; 973 974 codec: codec@1c22c00 { 975 #sound-dai-cells = <0>; 976 compatible = "allwinner,sun6i-a31-codec"; 977 reg = <0x01c22c00 0x400>; 978 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; 980 clock-names = "apb", "codec"; 981 resets = <&ccu RST_APB1_CODEC>; 982 dmas = <&dma 15>, <&dma 15>; 983 dma-names = "rx", "tx"; 984 status = "disabled"; 985 }; 986 987 timer@1c60000 { 988 compatible = "allwinner,sun6i-a31-hstimer", 989 "allwinner,sun7i-a20-hstimer"; 990 reg = <0x01c60000 0x1000>; 991 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&ccu CLK_AHB1_HSTIMER>; 996 resets = <&ccu RST_AHB1_HSTIMER>; 997 }; 998 999 spi0: spi@1c68000 { 1000 compatible = "allwinner,sun6i-a31-spi"; 1001 reg = <0x01c68000 0x1000>; 1002 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; 1004 clock-names = "ahb", "mod"; 1005 dmas = <&dma 23>, <&dma 23>; 1006 dma-names = "rx", "tx"; 1007 resets = <&ccu RST_AHB1_SPI0>; 1008 status = "disabled"; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 }; 1012 1013 spi1: spi@1c69000 { 1014 compatible = "allwinner,sun6i-a31-spi"; 1015 reg = <0x01c69000 0x1000>; 1016 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; 1018 clock-names = "ahb", "mod"; 1019 dmas = <&dma 24>, <&dma 24>; 1020 dma-names = "rx", "tx"; 1021 resets = <&ccu RST_AHB1_SPI1>; 1022 status = "disabled"; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 }; 1026 1027 spi2: spi@1c6a000 { 1028 compatible = "allwinner,sun6i-a31-spi"; 1029 reg = <0x01c6a000 0x1000>; 1030 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; 1032 clock-names = "ahb", "mod"; 1033 dmas = <&dma 25>, <&dma 25>; 1034 dma-names = "rx", "tx"; 1035 resets = <&ccu RST_AHB1_SPI2>; 1036 status = "disabled"; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 }; 1040 1041 spi3: spi@1c6b000 { 1042 compatible = "allwinner,sun6i-a31-spi"; 1043 reg = <0x01c6b000 0x1000>; 1044 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; 1046 clock-names = "ahb", "mod"; 1047 dmas = <&dma 26>, <&dma 26>; 1048 dma-names = "rx", "tx"; 1049 resets = <&ccu RST_AHB1_SPI3>; 1050 status = "disabled"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 }; 1054 1055 gic: interrupt-controller@1c81000 { 1056 compatible = "arm,gic-400"; 1057 reg = <0x01c81000 0x1000>, 1058 <0x01c82000 0x2000>, 1059 <0x01c84000 0x2000>, 1060 <0x01c86000 0x2000>; 1061 interrupt-controller; 1062 #interrupt-cells = <3>; 1063 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1064 }; 1065 1066 fe0: display-frontend@1e00000 { 1067 compatible = "allwinner,sun6i-a31-display-frontend"; 1068 reg = <0x01e00000 0x20000>; 1069 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, 1071 <&ccu CLK_DRAM_FE0>; 1072 clock-names = "ahb", "mod", 1073 "ram"; 1074 resets = <&ccu RST_AHB1_FE0>; 1075 1076 ports { 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 1080 fe0_out: port@1 { 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 reg = <1>; 1084 1085 fe0_out_be0: endpoint@0 { 1086 reg = <0>; 1087 remote-endpoint = <&be0_in_fe0>; 1088 }; 1089 1090 fe0_out_be1: endpoint@1 { 1091 reg = <1>; 1092 remote-endpoint = <&be1_in_fe0>; 1093 }; 1094 }; 1095 }; 1096 }; 1097 1098 fe1: display-frontend@1e20000 { 1099 compatible = "allwinner,sun6i-a31-display-frontend"; 1100 reg = <0x01e20000 0x20000>; 1101 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, 1103 <&ccu CLK_DRAM_FE1>; 1104 clock-names = "ahb", "mod", 1105 "ram"; 1106 resets = <&ccu RST_AHB1_FE1>; 1107 1108 ports { 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 1112 fe1_out: port@1 { 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 reg = <1>; 1116 1117 fe1_out_be0: endpoint@0 { 1118 reg = <0>; 1119 remote-endpoint = <&be0_in_fe1>; 1120 }; 1121 1122 fe1_out_be1: endpoint@1 { 1123 reg = <1>; 1124 remote-endpoint = <&be1_in_fe1>; 1125 }; 1126 }; 1127 }; 1128 }; 1129 1130 be1: display-backend@1e40000 { 1131 compatible = "allwinner,sun6i-a31-display-backend"; 1132 reg = <0x01e40000 0x10000>; 1133 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, 1135 <&ccu CLK_DRAM_BE1>; 1136 clock-names = "ahb", "mod", 1137 "ram"; 1138 resets = <&ccu RST_AHB1_BE1>; 1139 1140 ports { 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 1144 be1_in: port@0 { 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 reg = <0>; 1148 1149 be1_in_fe0: endpoint@0 { 1150 reg = <0>; 1151 remote-endpoint = <&fe0_out_be1>; 1152 }; 1153 1154 be1_in_fe1: endpoint@1 { 1155 reg = <1>; 1156 remote-endpoint = <&fe1_out_be1>; 1157 }; 1158 }; 1159 1160 be1_out: port@1 { 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 reg = <1>; 1164 1165 be1_out_drc1: endpoint@1 { 1166 reg = <1>; 1167 remote-endpoint = <&drc1_in_be1>; 1168 }; 1169 }; 1170 }; 1171 }; 1172 1173 drc1: drc@1e50000 { 1174 compatible = "allwinner,sun6i-a31-drc"; 1175 reg = <0x01e50000 0x10000>; 1176 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, 1178 <&ccu CLK_DRAM_DRC1>; 1179 clock-names = "ahb", "mod", 1180 "ram"; 1181 resets = <&ccu RST_AHB1_DRC1>; 1182 1183 ports { 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 1187 drc1_in: port@0 { 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 reg = <0>; 1191 1192 drc1_in_be1: endpoint@1 { 1193 reg = <1>; 1194 remote-endpoint = <&be1_out_drc1>; 1195 }; 1196 }; 1197 1198 drc1_out: port@1 { 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 reg = <1>; 1202 1203 drc1_out_tcon0: endpoint@0 { 1204 reg = <0>; 1205 remote-endpoint = <&tcon0_in_drc1>; 1206 }; 1207 1208 drc1_out_tcon1: endpoint@1 { 1209 reg = <1>; 1210 remote-endpoint = <&tcon1_in_drc1>; 1211 }; 1212 }; 1213 }; 1214 }; 1215 1216 be0: display-backend@1e60000 { 1217 compatible = "allwinner,sun6i-a31-display-backend"; 1218 reg = <0x01e60000 0x10000>; 1219 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, 1221 <&ccu CLK_DRAM_BE0>; 1222 clock-names = "ahb", "mod", 1223 "ram"; 1224 resets = <&ccu RST_AHB1_BE0>; 1225 1226 ports { 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 1230 be0_in: port@0 { 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 reg = <0>; 1234 1235 be0_in_fe0: endpoint@0 { 1236 reg = <0>; 1237 remote-endpoint = <&fe0_out_be0>; 1238 }; 1239 1240 be0_in_fe1: endpoint@1 { 1241 reg = <1>; 1242 remote-endpoint = <&fe1_out_be0>; 1243 }; 1244 }; 1245 1246 be0_out: port@1 { 1247 reg = <1>; 1248 1249 be0_out_drc0: endpoint { 1250 remote-endpoint = <&drc0_in_be0>; 1251 }; 1252 }; 1253 }; 1254 }; 1255 1256 drc0: drc@1e70000 { 1257 compatible = "allwinner,sun6i-a31-drc"; 1258 reg = <0x01e70000 0x10000>; 1259 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, 1261 <&ccu CLK_DRAM_DRC0>; 1262 clock-names = "ahb", "mod", 1263 "ram"; 1264 resets = <&ccu RST_AHB1_DRC0>; 1265 1266 ports { 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 1270 drc0_in: port@0 { 1271 reg = <0>; 1272 1273 drc0_in_be0: endpoint { 1274 remote-endpoint = <&be0_out_drc0>; 1275 }; 1276 }; 1277 1278 drc0_out: port@1 { 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 reg = <1>; 1282 1283 drc0_out_tcon0: endpoint@0 { 1284 reg = <0>; 1285 remote-endpoint = <&tcon0_in_drc0>; 1286 }; 1287 1288 drc0_out_tcon1: endpoint@1 { 1289 reg = <1>; 1290 remote-endpoint = <&tcon1_in_drc0>; 1291 }; 1292 }; 1293 }; 1294 }; 1295 1296 rtc: rtc@1f00000 { 1297 #clock-cells = <1>; 1298 compatible = "allwinner,sun6i-a31-rtc"; 1299 reg = <0x01f00000 0x54>; 1300 interrupt-parent = <&r_intc>; 1301 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&osc32k>; 1304 clock-output-names = "osc32k"; 1305 }; 1306 1307 r_intc: interrupt-controller@1f00c00 { 1308 compatible = "allwinner,sun6i-a31-r-intc"; 1309 interrupt-controller; 1310 #interrupt-cells = <3>; 1311 reg = <0x01f00c00 0x400>; 1312 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1313 }; 1314 1315 prcm@1f01400 { 1316 compatible = "allwinner,sun6i-a31-prcm"; 1317 reg = <0x01f01400 0x200>; 1318 1319 ar100: ar100_clk { 1320 compatible = "allwinner,sun6i-a31-ar100-clk"; 1321 #clock-cells = <0>; 1322 clocks = <&rtc 0>, <&osc24M>, 1323 <&ccu CLK_PLL_PERIPH>, 1324 <&ccu CLK_PLL_PERIPH>; 1325 clock-output-names = "ar100"; 1326 }; 1327 1328 ahb0: ahb0_clk { 1329 compatible = "fixed-factor-clock"; 1330 #clock-cells = <0>; 1331 clock-div = <1>; 1332 clock-mult = <1>; 1333 clocks = <&ar100>; 1334 clock-output-names = "ahb0"; 1335 }; 1336 1337 apb0: apb0_clk { 1338 compatible = "allwinner,sun6i-a31-apb0-clk"; 1339 #clock-cells = <0>; 1340 clocks = <&ahb0>; 1341 clock-output-names = "apb0"; 1342 }; 1343 1344 apb0_gates: apb0_gates_clk { 1345 compatible = "allwinner,sun6i-a31-apb0-gates-clk"; 1346 #clock-cells = <1>; 1347 clocks = <&apb0>; 1348 clock-output-names = "apb0_pio", "apb0_ir", 1349 "apb0_timer", "apb0_p2wi", 1350 "apb0_uart", "apb0_1wire", 1351 "apb0_i2c"; 1352 }; 1353 1354 ir_clk: ir_clk { 1355 #clock-cells = <0>; 1356 compatible = "allwinner,sun4i-a10-mod0-clk"; 1357 clocks = <&rtc 0>, <&osc24M>; 1358 clock-output-names = "ir"; 1359 }; 1360 1361 apb0_rst: apb0_rst { 1362 compatible = "allwinner,sun6i-a31-clock-reset"; 1363 #reset-cells = <1>; 1364 }; 1365 }; 1366 1367 cpucfg@1f01c00 { 1368 compatible = "allwinner,sun6i-a31-cpuconfig"; 1369 reg = <0x01f01c00 0x300>; 1370 }; 1371 1372 ir: ir@1f02000 { 1373 compatible = "allwinner,sun6i-a31-ir"; 1374 clocks = <&apb0_gates 1>, <&ir_clk>; 1375 clock-names = "apb", "ir"; 1376 resets = <&apb0_rst 1>; 1377 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1378 reg = <0x01f02000 0x40>; 1379 status = "disabled"; 1380 }; 1381 1382 r_pio: pinctrl@1f02c00 { 1383 compatible = "allwinner,sun6i-a31-r-pinctrl"; 1384 reg = <0x01f02c00 0x400>; 1385 interrupt-parent = <&r_intc>; 1386 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; 1389 clock-names = "apb", "hosc", "losc"; 1390 resets = <&apb0_rst 0>; 1391 gpio-controller; 1392 interrupt-controller; 1393 #interrupt-cells = <3>; 1394 #gpio-cells = <3>; 1395 1396 s_ir_rx_pin: s-ir-rx-pin { 1397 pins = "PL4"; 1398 function = "s_ir"; 1399 }; 1400 1401 s_p2wi_pins: s-p2wi-pins { 1402 pins = "PL0", "PL1"; 1403 function = "s_p2wi"; 1404 }; 1405 }; 1406 1407 p2wi: i2c@1f03400 { 1408 compatible = "allwinner,sun6i-a31-p2wi"; 1409 reg = <0x01f03400 0x400>; 1410 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&apb0_gates 3>; 1412 clock-frequency = <100000>; 1413 resets = <&apb0_rst 3>; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&s_p2wi_pins>; 1416 status = "disabled"; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 }; 1420 }; 1421}; 1422