1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/atmel-maxtouch.h>
5#include <dt-bindings/input/gpio-keys.h>
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/thermal/thermal.h>
8
9#include "tegra20.dtsi"
10#include "tegra20-cpu-opp.dtsi"
11#include "tegra20-cpu-opp-microvolt.dtsi"
12
13/ {
14	model = "Acer Iconia Tab A500";
15	compatible = "acer,picasso", "nvidia,tegra20";
16
17	aliases {
18		mmc0 = &sdmmc4; /* eMMC */
19		mmc1 = &sdmmc3; /* MicroSD */
20		mmc2 = &sdmmc1; /* WiFi */
21
22		rtc0 = &pmic;
23		rtc1 = "/rtc@7000e000";
24
25		serial0 = &uartd; /* Docking station */
26		serial1 = &uartc; /* Bluetooth */
27		serial2 = &uartb; /* GPS */
28	};
29
30	/*
31	 * The decompressor and also some bootloaders rely on a
32	 * pre-existing /chosen node to be available to insert the
33	 * command line and merge other ATAGS info.
34	 */
35	chosen {};
36
37	memory@0 {
38		reg = <0x00000000 0x40000000>;
39	};
40
41	reserved-memory {
42		#address-cells = <1>;
43		#size-cells = <1>;
44		ranges;
45
46		ramoops@2ffe0000 {
47			compatible = "ramoops";
48			reg = <0x2ffe0000 0x10000>;	/* 64kB */
49			console-size = <0x8000>;	/* 32kB */
50			record-size = <0x400>;		/*  1kB */
51			ecc-size = <16>;
52		};
53
54		linux,cma@30000000 {
55			compatible = "shared-dma-pool";
56			alloc-ranges = <0x30000000 0x10000000>;
57			size = <0x10000000>; /* 256MiB */
58			linux,cma-default;
59			reusable;
60		};
61	};
62
63	host1x@50000000 {
64		dc@54200000 {
65			rgb {
66				status = "okay";
67
68				port@0 {
69					lcd_output: endpoint {
70						remote-endpoint = <&lvds_encoder_input>;
71						bus-width = <18>;
72					};
73				};
74			};
75		};
76
77		hdmi@54280000 {
78			status = "okay";
79
80			vdd-supply = <&hdmi_vdd_reg>;
81			pll-supply = <&hdmi_pll_reg>;
82			hdmi-supply = <&vdd_5v0_sys>;
83
84			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
85			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
86				GPIO_ACTIVE_HIGH>;
87		};
88	};
89
90	pinmux@70000014 {
91		pinctrl-names = "default";
92		pinctrl-0 = <&state_default>;
93
94		state_default: pinmux {
95			ata {
96				nvidia,pins = "ata";
97				nvidia,function = "ide";
98			};
99			atb {
100				nvidia,pins = "atb", "gma", "gme";
101				nvidia,function = "sdio4";
102			};
103			atc {
104				nvidia,pins = "atc";
105				nvidia,function = "nand";
106			};
107			atd {
108				nvidia,pins = "atd", "ate", "gmb", "spia",
109					"spib", "spic";
110				nvidia,function = "gmi";
111			};
112			cdev1 {
113				nvidia,pins = "cdev1";
114				nvidia,function = "plla_out";
115			};
116			cdev2 {
117				nvidia,pins = "cdev2";
118				nvidia,function = "pllp_out4";
119			};
120			crtp {
121				nvidia,pins = "crtp", "lm1";
122				nvidia,function = "crt";
123			};
124			csus {
125				nvidia,pins = "csus";
126				nvidia,function = "vi_sensor_clk";
127			};
128			dap1 {
129				nvidia,pins = "dap1";
130				nvidia,function = "dap1";
131			};
132			dap2 {
133				nvidia,pins = "dap2";
134				nvidia,function = "dap2";
135			};
136			dap3 {
137				nvidia,pins = "dap3";
138				nvidia,function = "dap3";
139			};
140			dap4 {
141				nvidia,pins = "dap4";
142				nvidia,function = "dap4";
143			};
144			dta {
145				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
146				nvidia,function = "vi";
147			};
148			dtf {
149				nvidia,pins = "dtf";
150				nvidia,function = "i2c3";
151			};
152			gmc {
153				nvidia,pins = "gmc";
154				nvidia,function = "uartd";
155			};
156			gmd {
157				nvidia,pins = "gmd";
158				nvidia,function = "sflash";
159			};
160			gpu {
161				nvidia,pins = "gpu";
162				nvidia,function = "pwm";
163			};
164			gpu7 {
165				nvidia,pins = "gpu7";
166				nvidia,function = "rtck";
167			};
168			gpv {
169				nvidia,pins = "gpv", "slxa";
170				nvidia,function = "pcie";
171			};
172			hdint {
173				nvidia,pins = "hdint";
174				nvidia,function = "hdmi";
175			};
176			i2cp {
177				nvidia,pins = "i2cp";
178				nvidia,function = "i2cp";
179			};
180			irrx {
181				nvidia,pins = "irrx", "irtx";
182				nvidia,function = "uartb";
183			};
184			kbca {
185				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
186					"kbce", "kbcf";
187				nvidia,function = "kbc";
188			};
189			lcsn {
190				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
191					"lsdi", "lvp0";
192				nvidia,function = "rsvd4";
193			};
194			ld0 {
195				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
196					"ld5", "ld6", "ld7", "ld8", "ld9",
197					"ld10", "ld11", "ld12", "ld13", "ld14",
198					"ld15", "ld16", "ld17", "ldi", "lhp0",
199					"lhp1", "lhp2", "lhs", "lpp", "lsc0",
200					"lsc1", "lsck", "lsda", "lspi", "lvp1",
201					"lvs";
202				nvidia,function = "displaya";
203			};
204			owc {
205				nvidia,pins = "owc", "spdi", "spdo", "uac";
206				nvidia,function = "rsvd2";
207			};
208			pmc {
209				nvidia,pins = "pmc";
210				nvidia,function = "pwr_on";
211			};
212			rm {
213				nvidia,pins = "rm";
214				nvidia,function = "i2c1";
215			};
216			sdb {
217				nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
218				nvidia,function = "sdio3";
219			};
220			sdio1 {
221				nvidia,pins = "sdio1";
222				nvidia,function = "sdio1";
223			};
224			slxd {
225				nvidia,pins = "slxd";
226				nvidia,function = "spdif";
227			};
228			spid {
229				nvidia,pins = "spid", "spie", "spif";
230				nvidia,function = "spi1";
231			};
232			spig {
233				nvidia,pins = "spig", "spih";
234				nvidia,function = "spi2_alt";
235			};
236			uaa {
237				nvidia,pins = "uaa", "uab", "uda";
238				nvidia,function = "ulpi";
239			};
240			uad {
241				nvidia,pins = "uad";
242				nvidia,function = "irda";
243			};
244			uca {
245				nvidia,pins = "uca", "ucb";
246				nvidia,function = "uartc";
247			};
248			conf_ata {
249				nvidia,pins = "ata", "atb", "atc", "atd",
250					"cdev1", "cdev2", "csus", "dap1",
251					"dap4", "dte", "dtf", "gma", "gmc",
252					"gme", "gpu", "gpu7", "gpv", "i2cp",
253					"irrx", "irtx", "pta", "rm",
254					"sdc", "sdd", "slxc", "slxd", "slxk",
255					"spdi", "spdo", "uac", "uad", "uda";
256				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
257				nvidia,tristate = <TEGRA_PIN_DISABLE>;
258			};
259			conf_ate {
260				nvidia,pins = "ate", "dap2", "dap3",
261					"gmd", "owc", "spia", "spib", "spic",
262					"spid", "spie";
263				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264				nvidia,tristate = <TEGRA_PIN_ENABLE>;
265			};
266			conf_ck32 {
267				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
268					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
269				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
270			};
271			conf_crtp {
272				nvidia,pins = "crtp", "gmb", "slxa", "spig",
273					"spih";
274				nvidia,pull = <TEGRA_PIN_PULL_UP>;
275				nvidia,tristate = <TEGRA_PIN_ENABLE>;
276			};
277			conf_dta {
278				nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
279				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
280				nvidia,tristate = <TEGRA_PIN_DISABLE>;
281			};
282			conf_dte {
283				nvidia,pins = "spif";
284				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
285				nvidia,tristate = <TEGRA_PIN_ENABLE>;
286			};
287			conf_hdint {
288				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
289					"lpw1", "lsck", "lsda", "lsdi",
290					"lvp0";
291				nvidia,tristate = <TEGRA_PIN_ENABLE>;
292			};
293			conf_kbca {
294				nvidia,pins = "kbca", "kbcc", "kbcd",
295					"kbce", "kbcf", "sdio1", "uaa",
296					"uab", "uca", "ucb";
297				nvidia,pull = <TEGRA_PIN_PULL_UP>;
298				nvidia,tristate = <TEGRA_PIN_DISABLE>;
299			};
300			conf_lc {
301				nvidia,pins = "lc", "ls";
302				nvidia,pull = <TEGRA_PIN_PULL_UP>;
303			};
304			conf_ld0 {
305				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
306					"ld5", "ld6", "ld7", "ld8", "ld9",
307					"ld10", "ld11", "ld12", "ld13", "ld14",
308					"ld15", "ld16", "ld17", "ldi", "lhp0",
309					"lhp1", "lhp2", "lhs", "lm0", "lpp",
310					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
311					"lvp1", "lvs", "pmc", "sdb";
312				nvidia,tristate = <TEGRA_PIN_DISABLE>;
313			};
314			conf_ld17_0 {
315				nvidia,pins = "ld17_0";
316				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
317			};
318			drive_ddc {
319				nvidia,pins = "drive_ddc",
320						"drive_vi1",
321						"drive_sdio1";
322				nvidia,pull-up-strength = <31>;
323				nvidia,pull-down-strength = <31>;
324				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
325				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
326				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
327				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
328				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
329			};
330			drive_dbg {
331				nvidia,pins = "drive_dbg",
332						"drive_vi2",
333						"drive_at1",
334						"drive_ao1";
335				nvidia,pull-up-strength = <31>;
336				nvidia,pull-down-strength = <31>;
337				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
338				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
339				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
340				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
341				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
342			};
343		};
344
345		state_i2cmux_ddc: pinmux_i2cmux_ddc {
346			ddc {
347				nvidia,pins = "ddc";
348				nvidia,function = "i2c2";
349			};
350			pta {
351				nvidia,pins = "pta";
352				nvidia,function = "rsvd4";
353			};
354		};
355
356		state_i2cmux_pta: pinmux_i2cmux_pta {
357			ddc {
358				nvidia,pins = "ddc";
359				nvidia,function = "rsvd4";
360			};
361			pta {
362				nvidia,pins = "pta";
363				nvidia,function = "i2c2";
364			};
365		};
366
367		state_i2cmux_idle: pinmux_i2cmux_idle {
368			ddc {
369				nvidia,pins = "ddc";
370				nvidia,function = "rsvd4";
371			};
372			pta {
373				nvidia,pins = "pta";
374				nvidia,function = "rsvd4";
375			};
376		};
377	};
378
379	tegra_i2s1: i2s@70002800 {
380		status = "okay";
381	};
382
383	uartb: serial@70006040 {
384		compatible = "nvidia,tegra20-hsuart";
385		/* GPS BCM4751 */
386	};
387
388	uartc: serial@70006200 {
389		compatible = "nvidia,tegra20-hsuart";
390		status = "okay";
391
392		/* Azurewave AW-NH665 BCM4329B1 */
393		bluetooth {
394			compatible = "brcm,bcm4329-bt";
395
396			interrupt-parent = <&gpio>;
397			interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
398			interrupt-names = "host-wakeup";
399
400			/* PLLP 216MHz / 16 / 4 */
401			max-speed = <3375000>;
402
403			clocks = <&rtc_32k_wifi>;
404			clock-names = "txco";
405
406			vbat-supply  = <&vdd_3v3_sys>;
407			vddio-supply = <&vdd_1v8_sys>;
408
409			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
410			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
411		};
412	};
413
414	uartd: serial@70006300 {
415		/* Docking station */
416	};
417
418	i2c@7000c000 {
419		clock-frequency = <400000>;
420		status = "okay";
421
422		wm8903: audio-codec@1a {
423			compatible = "wlf,wm8903";
424			reg = <0x1a>;
425
426			interrupt-parent = <&gpio>;
427			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>;
428
429			gpio-controller;
430			#gpio-cells = <2>;
431
432			micdet-cfg = <0>;
433			micdet-delay = <100>;
434
435			gpio-cfg = <
436				0x0000 /* MIC_LR_OUT#    GPIO, output, low */
437				0x0000 /* FM2018-enable  GPIO, output, low */
438				0x0000 /* Speaker-enable GPIO, output, low */
439				0x0200 /* Interrupt, output */
440				0x01a0 /* BCLK, input, active high */
441			>;
442
443			AVDD-supply  = <&vdd_1v8_sys>;
444			CPVDD-supply = <&vdd_1v8_sys>;
445			DBVDD-supply = <&vdd_1v8_sys>;
446			DCVDD-supply = <&vdd_1v8_sys>;
447		};
448
449		touchscreen@4c {
450			compatible = "atmel,maxtouch";
451			reg = <0x4c>;
452
453			interrupt-parent = <&gpio>;
454			interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
455
456			reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
457
458			vdda-supply = <&vdd_3v3_sys>;
459			vdd-supply  = <&vdd_3v3_sys>;
460
461			atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
462		};
463
464		gyroscope@68 {
465			compatible = "invensense,mpu3050";
466			reg = <0x68>;
467
468			interrupt-parent = <&gpio>;
469			interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
470
471			vdd-supply    = <&vdd_3v3_sys>;
472			vlogic-supply = <&vdd_1v8_sys>;
473
474			mount-matrix =	 "0",  "1",  "0",
475					 "1",  "0",  "0",
476					 "0",  "0", "-1";
477
478			i2c-gate {
479				#address-cells = <1>;
480				#size-cells = <0>;
481
482				accelerometer@f {
483					compatible = "kionix,kxtf9";
484					reg = <0x0f>;
485
486					interrupt-parent = <&gpio>;
487					interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
488
489					vdd-supply   = <&vdd_1v8_sys>;
490					vddio-supply = <&vdd_1v8_sys>;
491
492					mount-matrix =	 "0",  "1",  "0",
493							 "1",  "0",  "0",
494							 "0",  "0", "-1";
495				};
496			};
497		};
498	};
499
500	i2c@7000c400 {
501		clock-frequency = <10000>;
502		status = "okay";
503	};
504
505	i2cmux {
506		compatible = "i2c-mux-pinctrl";
507		#address-cells = <1>;
508		#size-cells = <0>;
509
510		i2c-parent = <&{/i2c@7000c400}>;
511
512		pinctrl-names = "ddc", "pta", "idle";
513		pinctrl-0 = <&state_i2cmux_ddc>;
514		pinctrl-1 = <&state_i2cmux_pta>;
515		pinctrl-2 = <&state_i2cmux_idle>;
516
517		hdmi_ddc: i2c@0 {
518			reg = <0>;
519			#address-cells = <1>;
520			#size-cells = <0>;
521		};
522
523		panel_ddc: i2c@1 {
524			reg = <1>;
525			#address-cells = <1>;
526			#size-cells = <0>;
527
528			embedded-controller@58 {
529				compatible = "acer,a500-iconia-ec", "ene,kb930";
530				reg = <0x58>;
531
532				system-power-controller;
533
534				monitored-battery = <&bat1010>;
535				power-supplies = <&mains>;
536			};
537		};
538	};
539
540	pwm: pwm@7000a000 {
541		status = "okay";
542	};
543
544	i2c@7000d000 {
545		clock-frequency = <100000>;
546		status = "okay";
547
548		magnetometer@c {
549			compatible = "asahi-kasei,ak8975";
550			reg = <0x0c>;
551
552			interrupt-parent = <&gpio>;
553			interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
554
555			vdd-supply = <&vdd_3v3_sys>;
556			vid-supply = <&vdd_1v8_sys>;
557
558			mount-matrix =	"1",  "0",  "0",
559					"0", "-1",  "0",
560					"0",  "0", "-1";
561		};
562
563		pmic: pmic@34 {
564			compatible = "ti,tps6586x";
565			reg = <0x34>;
566
567			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
568
569			#gpio-cells = <2>;
570			gpio-controller;
571
572			sys-supply       = <&vdd_5v0_sys>;
573			vin-sm0-supply   = <&sys_reg>;
574			vin-sm1-supply   = <&sys_reg>;
575			vin-sm2-supply   = <&sys_reg>;
576			vinldo01-supply  = <&sm2_reg>;
577			vinldo23-supply  = <&sm2_reg>;
578			vinldo4-supply   = <&sm2_reg>;
579			vinldo678-supply = <&sm2_reg>;
580			vinldo9-supply   = <&sm2_reg>;
581
582			regulators {
583				sys_reg: sys {
584					regulator-name = "vdd_sys";
585					regulator-always-on;
586				};
587
588				vdd_core: sm0 {
589					regulator-name = "vdd_sm0,vdd_core";
590					regulator-min-microvolt = <950000>;
591					regulator-max-microvolt = <1300000>;
592					regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
593					regulator-coupled-max-spread = <170000 550000>;
594					regulator-always-on;
595					regulator-boot-on;
596
597					nvidia,tegra-core-regulator;
598				};
599
600				vdd_cpu: sm1 {
601					regulator-name = "vdd_sm1,vdd_cpu";
602					regulator-min-microvolt = <750000>;
603					regulator-max-microvolt = <1125000>;
604					regulator-coupled-with = <&vdd_core &rtc_vdd>;
605					regulator-coupled-max-spread = <550000 550000>;
606					regulator-always-on;
607					regulator-boot-on;
608
609					nvidia,tegra-cpu-regulator;
610				};
611
612				sm2_reg: sm2 {
613					regulator-name = "vdd_sm2,vin_ldo*";
614					regulator-min-microvolt = <3700000>;
615					regulator-max-microvolt = <3700000>;
616					regulator-always-on;
617				};
618
619				/* LDO0 is not connected to anything */
620
621				ldo1 {
622					regulator-name = "vdd_ldo1,avdd_pll*";
623					regulator-min-microvolt = <1100000>;
624					regulator-max-microvolt = <1100000>;
625					regulator-always-on;
626					regulator-boot-on;
627				};
628
629				rtc_vdd: ldo2 {
630					regulator-name = "vdd_ldo2,vdd_rtc";
631					regulator-min-microvolt = <950000>;
632					regulator-max-microvolt = <1300000>;
633					regulator-coupled-with = <&vdd_core &vdd_cpu>;
634					regulator-coupled-max-spread = <170000 550000>;
635					regulator-always-on;
636					regulator-boot-on;
637
638					nvidia,tegra-rtc-regulator;
639				};
640
641				ldo3 {
642					regulator-name = "vdd_ldo3,avdd_usb*";
643					regulator-min-microvolt = <3300000>;
644					regulator-max-microvolt = <3300000>;
645					regulator-always-on;
646				};
647
648				ldo4 {
649					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
650					regulator-min-microvolt = <1800000>;
651					regulator-max-microvolt = <1800000>;
652					regulator-always-on;
653					regulator-boot-on;
654				};
655
656				vcore_emmc: ldo5 {
657					regulator-name = "vdd_ldo5,vcore_mmc";
658					regulator-min-microvolt = <2850000>;
659					regulator-max-microvolt = <2850000>;
660					regulator-always-on;
661				};
662
663				avdd_vdac_reg: ldo6 {
664					regulator-name = "vdd_ldo6,avdd_vdac";
665					regulator-min-microvolt = <2850000>;
666					regulator-max-microvolt = <2850000>;
667				};
668
669				hdmi_vdd_reg: ldo7 {
670					regulator-name = "vdd_ldo7,avdd_hdmi";
671					regulator-min-microvolt = <3300000>;
672					regulator-max-microvolt = <3300000>;
673				};
674
675				hdmi_pll_reg: ldo8 {
676					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
677					regulator-min-microvolt = <1800000>;
678					regulator-max-microvolt = <1800000>;
679				};
680
681				ldo9 {
682					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
683					regulator-min-microvolt = <2850000>;
684					regulator-max-microvolt = <2850000>;
685					regulator-always-on;
686					regulator-boot-on;
687				};
688
689				ldo_rtc {
690					regulator-name = "vdd_rtc_out,vdd_cell";
691					regulator-min-microvolt = <3300000>;
692					regulator-max-microvolt = <3300000>;
693					regulator-always-on;
694					regulator-boot-on;
695				};
696			};
697		};
698
699		nct1008: temperature-sensor@4c {
700			compatible = "onnn,nct1008";
701			reg = <0x4c>;
702			vcc-supply = <&vdd_3v3_sys>;
703
704			interrupt-parent = <&gpio>;
705			interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
706
707			#thermal-sensor-cells = <1>;
708		};
709	};
710
711	pmc@7000e400 {
712		nvidia,invert-interrupt;
713		nvidia,suspend-mode = <1>;
714		nvidia,cpu-pwr-good-time = <2000>;
715		nvidia,cpu-pwr-off-time = <100>;
716		nvidia,core-pwr-good-time = <3845 3845>;
717		nvidia,core-pwr-off-time = <458>;
718		nvidia,sys-clock-req-active-high;
719	};
720
721	usb@c5000000 {
722		compatible = "nvidia,tegra20-udc";
723		status = "okay";
724		dr_mode = "peripheral";
725	};
726
727	usb-phy@c5000000 {
728		status = "okay";
729		dr_mode = "peripheral";
730		nvidia,xcvr-setup-use-fuses;
731		nvidia,xcvr-lsfslew = <2>;
732		nvidia,xcvr-lsrslew = <2>;
733	};
734
735	usb@c5008000 {
736		status = "okay";
737	};
738
739	usb-phy@c5008000 {
740		status = "okay";
741		nvidia,xcvr-setup-use-fuses;
742		nvidia,xcvr-lsfslew = <2>;
743		nvidia,xcvr-lsrslew = <2>;
744		vbus-supply = <&vdd_5v0_sys>;
745	};
746
747	brcm_wifi_pwrseq: wifi-pwrseq {
748		compatible = "mmc-pwrseq-simple";
749
750		clocks = <&rtc_32k_wifi>;
751		clock-names = "ext_clock";
752
753		reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
754		post-power-on-delay-ms = <300>;
755		power-off-delay-us = <300>;
756	};
757
758	sdmmc1: mmc@c8000000 {
759		status = "okay";
760
761		#address-cells = <1>;
762		#size-cells = <0>;
763
764		assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
765		assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
766		assigned-clock-rates = <50000000>;
767
768		max-frequency = <50000000>;
769		keep-power-in-suspend;
770		bus-width = <4>;
771		non-removable;
772
773		mmc-pwrseq = <&brcm_wifi_pwrseq>;
774		vmmc-supply = <&vdd_3v3_sys>;
775		vqmmc-supply = <&vdd_1v8_sys>;
776
777		/* Azurewave AW-NH611 BCM4329 */
778		wifi@1 {
779			reg = <1>;
780			compatible = "brcm,bcm4329-fmac";
781			interrupt-parent = <&gpio>;
782			interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
783			interrupt-names = "host-wake";
784		};
785	};
786
787	sdmmc3: mmc@c8000400 {
788		status = "okay";
789		bus-width = <4>;
790		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
791		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
792		vmmc-supply = <&vdd_3v3_sys>;
793		vqmmc-supply = <&vdd_3v3_sys>;
794	};
795
796	sdmmc4: mmc@c8000600 {
797		status = "okay";
798		bus-width = <8>;
799		vmmc-supply = <&vcore_emmc>;
800		vqmmc-supply = <&vdd_3v3_sys>;
801		non-removable;
802	};
803
804	mains: ac-adapter-detect {
805		compatible = "gpio-charger";
806		charger-type = "mains";
807		gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
808	};
809
810	backlight: backlight {
811		compatible = "pwm-backlight";
812
813		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
814		power-supply = <&vdd_3v3_sys>;
815		pwms = <&pwm 2 41667>;
816
817		brightness-levels = <7 255>;
818		num-interpolated-steps = <248>;
819		default-brightness-level = <20>;
820	};
821
822	bat1010: battery-2s1p {
823		compatible = "simple-battery";
824		charge-full-design-microamp-hours = <3260000>;
825		energy-full-design-microwatt-hours = <24000000>;
826		operating-range-celsius = <0 40>;
827	};
828
829	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
830	clk32k_in: clock@0 {
831		compatible = "fixed-clock";
832		#clock-cells = <0>;
833		clock-frequency = <32768>;
834		clock-output-names = "tps658621-out32k";
835	};
836
837	/*
838	 * This standalone onboard fixed-clock always-ON 32KHz
839	 * oscillator is used as a reference clock-source by the
840	 * Azurewave WiFi/BT module.
841	 */
842	rtc_32k_wifi: clock@1 {
843		compatible = "fixed-clock";
844		#clock-cells = <0>;
845		clock-frequency = <32768>;
846		clock-output-names = "kk3270032";
847	};
848
849	cpus {
850		cpu0: cpu@0 {
851			cpu-supply = <&vdd_cpu>;
852			operating-points-v2 = <&cpu0_opp_table>;
853			#cooling-cells = <2>;
854		};
855
856		cpu1: cpu@1 {
857			cpu-supply = <&vdd_cpu>;
858			operating-points-v2 = <&cpu0_opp_table>;
859			#cooling-cells = <2>;
860		};
861	};
862
863	display-panel {
864		compatible = "auo,b101ew05", "panel-lvds";
865
866		ddc-i2c-bus = <&panel_ddc>;
867		power-supply = <&vdd_pnl>;
868		backlight = <&backlight>;
869
870		width-mm = <218>;
871		height-mm = <135>;
872
873		data-mapping = "jeida-18";
874
875		panel-timing {
876			clock-frequency = <71200000>;
877			hactive = <1280>;
878			vactive = <800>;
879			hfront-porch = <8>;
880			hback-porch = <18>;
881			hsync-len = <184>;
882			vsync-len = <3>;
883			vfront-porch = <4>;
884			vback-porch = <8>;
885		};
886
887		port {
888			panel_input: endpoint {
889				remote-endpoint = <&lvds_encoder_output>;
890			};
891		};
892	};
893
894	gpio-keys {
895		compatible = "gpio-keys";
896
897		power {
898			label = "Power";
899			gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
900			linux,code = <KEY_POWER>;
901			debounce-interval = <10>;
902			wakeup-event-action = <EV_ACT_ASSERTED>;
903			wakeup-source;
904		};
905
906		rotation-lock {
907			label = "Rotate-lock";
908			gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
909			linux,code = <SW_ROTATE_LOCK>;
910			linux,input-type = <EV_SW>;
911			debounce-interval = <10>;
912		};
913
914		volume-up {
915			label = "Volume Up";
916			gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
917			linux,code = <KEY_VOLUMEUP>;
918			debounce-interval = <10>;
919			wakeup-event-action = <EV_ACT_ASSERTED>;
920			wakeup-source;
921		};
922
923		volume-down {
924			label = "Volume Down";
925			gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
926			linux,code = <KEY_VOLUMEDOWN>;
927			debounce-interval = <10>;
928			wakeup-event-action = <EV_ACT_ASSERTED>;
929			wakeup-source;
930		};
931	};
932
933	haptic-feedback {
934		compatible = "gpio-vibrator";
935		enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
936		vcc-supply = <&vdd_3v3_sys>;
937	};
938
939	lvds-encoder {
940		compatible = "ti,sn75lvds83", "lvds-encoder";
941
942		powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
943		power-supply = <&vdd_3v3_sys>;
944
945		ports {
946			#address-cells = <1>;
947			#size-cells = <0>;
948
949			port@0 {
950				reg = <0>;
951
952				lvds_encoder_input: endpoint {
953					remote-endpoint = <&lcd_output>;
954				};
955			};
956
957			port@1 {
958				reg = <1>;
959
960				lvds_encoder_output: endpoint {
961					remote-endpoint = <&panel_input>;
962				};
963			};
964		};
965	};
966
967	vdd_5v0_sys: regulator@0 {
968		compatible = "regulator-fixed";
969		regulator-name = "vdd_5v0";
970		regulator-min-microvolt = <5000000>;
971		regulator-max-microvolt = <5000000>;
972		regulator-always-on;
973	};
974
975	vdd_3v3_sys: regulator@1 {
976		compatible = "regulator-fixed";
977		regulator-name = "vdd_3v3_vs";
978		regulator-min-microvolt = <3300000>;
979		regulator-max-microvolt = <3300000>;
980		regulator-always-on;
981		vin-supply = <&vdd_5v0_sys>;
982	};
983
984	vdd_1v8_sys: regulator@2 {
985		compatible = "regulator-fixed";
986		regulator-name = "vdd_1v8_vs";
987		regulator-min-microvolt = <1800000>;
988		regulator-max-microvolt = <1800000>;
989		regulator-always-on;
990		vin-supply = <&vdd_5v0_sys>;
991	};
992
993	vdd_pnl: regulator@3 {
994		compatible = "regulator-fixed";
995		regulator-name = "vdd_panel";
996		regulator-min-microvolt = <3300000>;
997		regulator-max-microvolt = <3300000>;
998		regulator-enable-ramp-delay = <300000>;
999		gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
1000		enable-active-high;
1001		vin-supply = <&vdd_5v0_sys>;
1002	};
1003
1004	sound {
1005		compatible = "nvidia,tegra-audio-wm8903-picasso",
1006			     "nvidia,tegra-audio-wm8903";
1007		nvidia,model = "Acer Iconia Tab A500 WM8903";
1008
1009		nvidia,audio-routing =
1010			"Headphone Jack", "HPOUTR",
1011			"Headphone Jack", "HPOUTL",
1012			"Int Spk", "LINEOUTL",
1013			"Int Spk", "LINEOUTR",
1014			"Mic Jack", "MICBIAS",
1015			"IN2L", "Mic Jack",
1016			"IN2R", "Mic Jack",
1017			"IN1L", "Int Mic",
1018			"IN1R", "Int Mic";
1019
1020		nvidia,i2s-controller = <&tegra_i2s1>;
1021		nvidia,audio-codec = <&wm8903>;
1022
1023		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
1024		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1025		nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
1026		nvidia,headset;
1027
1028		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
1029			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
1030			 <&tegra_car TEGRA20_CLK_CDEV1>;
1031		clock-names = "pll_a", "pll_a_out0", "mclk";
1032	};
1033
1034	thermal-zones {
1035		/*
1036		 * NCT1008 has two sensors:
1037		 *
1038		 *	0: internal that monitors ambient/skin temperature
1039		 *	1: external that is connected to the CPU's diode
1040		 *
1041		 * Ideally we should use userspace thermal governor,
1042		 * but it's a much more complex solution.  The "skin"
1043		 * zone is a simpler solution which prevents A500 from
1044		 * getting too hot from a user's tactile perspective.
1045		 * The CPU zone is intended to protect silicon from damage.
1046		 */
1047
1048		skin-thermal {
1049			polling-delay-passive = <1000>; /* milliseconds */
1050			polling-delay = <5000>; /* milliseconds */
1051
1052			thermal-sensors = <&nct1008 0>;
1053
1054			trips {
1055				trip0: skin-alert {
1056					/* start throttling at 60C */
1057					temperature = <60000>;
1058					hysteresis = <200>;
1059					type = "passive";
1060				};
1061
1062				trip1: skin-crit {
1063					/* shut down at 70C */
1064					temperature = <70000>;
1065					hysteresis = <2000>;
1066					type = "critical";
1067				};
1068			};
1069
1070			cooling-maps {
1071				map0 {
1072					trip = <&trip0>;
1073					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1074							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1075				};
1076			};
1077		};
1078
1079		cpu-thermal {
1080			polling-delay-passive = <1000>; /* milliseconds */
1081			polling-delay = <5000>; /* milliseconds */
1082
1083			thermal-sensors = <&nct1008 1>;
1084
1085			trips {
1086				trip2: cpu-alert {
1087					/* throttle at 85C until temperature drops to 84.8C */
1088					temperature = <85000>;
1089					hysteresis = <200>;
1090					type = "passive";
1091				};
1092
1093				trip3: cpu-crit {
1094					/* shut down at 90C */
1095					temperature = <90000>;
1096					hysteresis = <2000>;
1097					type = "critical";
1098				};
1099			};
1100
1101			cooling-maps {
1102				map1 {
1103					trip = <&trip2>;
1104					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1105							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1106				};
1107			};
1108		};
1109	};
1110
1111	memory-controller@7000f400 {
1112		nvidia,use-ram-code;
1113
1114		emc-tables@0 {
1115			nvidia,ram-code = <0>; /* elpida-8gb */
1116			reg = <0>;
1117
1118			#address-cells = <1>;
1119			#size-cells = <0>;
1120
1121			emc-table@25000 {
1122				reg = <25000>;
1123				compatible = "nvidia,tegra20-emc-table";
1124				clock-frequency = <25000>;
1125				nvidia,emc-registers = <0x00000002 0x00000006
1126					0x00000003 0x00000003 0x00000006 0x00000004
1127					0x00000002 0x00000009 0x00000003 0x00000003
1128					0x00000002 0x00000002 0x00000002 0x00000004
1129					0x00000003 0x00000008 0x0000000b 0x0000004d
1130					0x00000000 0x00000003 0x00000003 0x00000003
1131					0x00000008 0x00000001 0x0000000a 0x00000004
1132					0x00000003 0x00000008 0x00000004 0x00000006
1133					0x00000002 0x00000068 0x00000000 0x00000003
1134					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1135					0x00070000 0x00000000 0x00000000 0x00000003
1136					0x00000000 0x00000000 0x00000000 0x00000000>;
1137			};
1138
1139			emc-table@50000 {
1140				reg = <50000>;
1141				compatible = "nvidia,tegra20-emc-table";
1142				clock-frequency = <50000>;
1143				nvidia,emc-registers = <0x00000003 0x00000007
1144					0x00000003 0x00000003 0x00000006 0x00000004
1145					0x00000002 0x00000009 0x00000003 0x00000003
1146					0x00000002 0x00000002 0x00000002 0x00000005
1147					0x00000003 0x00000008 0x0000000b 0x0000009f
1148					0x00000000 0x00000003 0x00000003 0x00000003
1149					0x00000008 0x00000001 0x0000000a 0x00000007
1150					0x00000003 0x00000008 0x00000004 0x00000006
1151					0x00000002 0x000000d0 0x00000000 0x00000000
1152					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1153					0x00070000 0x00000000 0x00000000 0x00000005
1154					0x00000000 0x00000000 0x00000000 0x00000000>;
1155			};
1156
1157			emc-table@75000 {
1158				reg = <75000>;
1159				compatible = "nvidia,tegra20-emc-table";
1160				clock-frequency = <75000>;
1161				nvidia,emc-registers = <0x00000005 0x0000000a
1162					0x00000004 0x00000003 0x00000006 0x00000004
1163					0x00000002 0x00000009 0x00000003 0x00000003
1164					0x00000002 0x00000002 0x00000002 0x00000005
1165					0x00000003 0x00000008 0x0000000b 0x000000ff
1166					0x00000000 0x00000003 0x00000003 0x00000003
1167					0x00000008 0x00000001 0x0000000a 0x0000000b
1168					0x00000003 0x00000008 0x00000004 0x00000006
1169					0x00000002 0x00000138 0x00000000 0x00000000
1170					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1171					0x00070000 0x00000000 0x00000000 0x00000007
1172					0x00000000 0x00000000 0x00000000 0x00000000>;
1173			};
1174
1175			emc-table@150000 {
1176				reg = <150000>;
1177				compatible = "nvidia,tegra20-emc-table";
1178				clock-frequency = <150000>;
1179				nvidia,emc-registers = <0x00000009 0x00000014
1180					0x00000007 0x00000003 0x00000006 0x00000004
1181					0x00000002 0x00000009 0x00000003 0x00000003
1182					0x00000002 0x00000002 0x00000002 0x00000005
1183					0x00000003 0x00000008 0x0000000b 0x0000021f
1184					0x00000000 0x00000003 0x00000003 0x00000003
1185					0x00000008 0x00000001 0x0000000a 0x00000015
1186					0x00000003 0x00000008 0x00000004 0x00000006
1187					0x00000002 0x00000270 0x00000000 0x00000001
1188					0x00000000 0x00000000 0x00000282 0xa07c04ae
1189					0x007dd510 0x00000000 0x00000000 0x0000000e
1190					0x00000000 0x00000000 0x00000000 0x00000000>;
1191			};
1192
1193			emc-table@300000 {
1194				reg = <300000>;
1195				compatible = "nvidia,tegra20-emc-table";
1196				clock-frequency = <300000>;
1197				nvidia,emc-registers = <0x00000012 0x00000027
1198					0x0000000d 0x00000006 0x00000007 0x00000005
1199					0x00000003 0x00000009 0x00000006 0x00000006
1200					0x00000003 0x00000003 0x00000002 0x00000006
1201					0x00000003 0x00000009 0x0000000c 0x0000045f
1202					0x00000000 0x00000004 0x00000004 0x00000006
1203					0x00000008 0x00000001 0x0000000e 0x0000002a
1204					0x00000003 0x0000000f 0x00000007 0x00000005
1205					0x00000002 0x000004e1 0x00000005 0x00000002
1206					0x00000000 0x00000000 0x00000282 0xe059048b
1207					0x007e1510 0x00000000 0x00000000 0x0000001b
1208					0x00000000 0x00000000 0x00000000 0x00000000>;
1209			};
1210		};
1211
1212		emc-tables@1 {
1213			nvidia,ram-code = <1>; /* elpida-4gb */
1214			reg = <1>;
1215
1216			#address-cells = <1>;
1217			#size-cells = <0>;
1218
1219			emc-table@25000 {
1220				reg = <25000>;
1221				compatible = "nvidia,tegra20-emc-table";
1222				clock-frequency = <25000>;
1223				nvidia,emc-registers = <0x00000002 0x00000006
1224					0x00000003 0x00000003 0x00000006 0x00000004
1225					0x00000002 0x00000009 0x00000003 0x00000003
1226					0x00000002 0x00000002 0x00000002 0x00000004
1227					0x00000003 0x00000008 0x0000000b 0x0000004d
1228					0x00000000 0x00000003 0x00000003 0x00000003
1229					0x00000008 0x00000001 0x0000000a 0x00000004
1230					0x00000003 0x00000008 0x00000004 0x00000006
1231					0x00000002 0x00000068 0x00000000 0x00000003
1232					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1233					0x0007c000 0x00000000 0x00000000 0x00000003
1234					0x00000000 0x00000000 0x00000000 0x00000000>;
1235			};
1236
1237			emc-table@50000 {
1238				reg = <50000>;
1239				compatible = "nvidia,tegra20-emc-table";
1240				clock-frequency = <50000>;
1241				nvidia,emc-registers = <0x00000003 0x00000007
1242					0x00000003 0x00000003 0x00000006 0x00000004
1243					0x00000002 0x00000009 0x00000003 0x00000003
1244					0x00000002 0x00000002 0x00000002 0x00000005
1245					0x00000003 0x00000008 0x0000000b 0x0000009f
1246					0x00000000 0x00000003 0x00000003 0x00000003
1247					0x00000008 0x00000001 0x0000000a 0x00000007
1248					0x00000003 0x00000008 0x00000004 0x00000006
1249					0x00000002 0x000000d0 0x00000000 0x00000000
1250					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1251					0x0007c000 0x00000000 0x00000000 0x00000005
1252					0x00000000 0x00000000 0x00000000 0x00000000>;
1253			};
1254
1255			emc-table@75000 {
1256				reg = <75000>;
1257				compatible = "nvidia,tegra20-emc-table";
1258				clock-frequency = <75000>;
1259				nvidia,emc-registers = <0x00000005 0x0000000a
1260					0x00000004 0x00000003 0x00000006 0x00000004
1261					0x00000002 0x00000009 0x00000003 0x00000003
1262					0x00000002 0x00000002 0x00000002 0x00000005
1263					0x00000003 0x00000008 0x0000000b 0x000000ff
1264					0x00000000 0x00000003 0x00000003 0x00000003
1265					0x00000008 0x00000001 0x0000000a 0x0000000b
1266					0x00000003 0x00000008 0x00000004 0x00000006
1267					0x00000002 0x00000138 0x00000000 0x00000000
1268					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1269					0x0007c000 0x00000000 0x00000000 0x00000007
1270					0x00000000 0x00000000 0x00000000 0x00000000>;
1271			};
1272
1273			emc-table@150000 {
1274				reg = <150000>;
1275				compatible = "nvidia,tegra20-emc-table";
1276				clock-frequency = <150000>;
1277				nvidia,emc-registers = <0x00000009 0x00000014
1278					0x00000007 0x00000003 0x00000006 0x00000004
1279					0x00000002 0x00000009 0x00000003 0x00000003
1280					0x00000002 0x00000002 0x00000002 0x00000005
1281					0x00000003 0x00000008 0x0000000b 0x0000021f
1282					0x00000000 0x00000003 0x00000003 0x00000003
1283					0x00000008 0x00000001 0x0000000a 0x00000015
1284					0x00000003 0x00000008 0x00000004 0x00000006
1285					0x00000002 0x00000270 0x00000000 0x00000001
1286					0x00000000 0x00000000 0x00000282 0xa07c04ae
1287					0x007e4010 0x00000000 0x00000000 0x0000000e
1288					0x00000000 0x00000000 0x00000000 0x00000000>;
1289			};
1290
1291			emc-table@300000 {
1292				reg = <300000>;
1293				compatible = "nvidia,tegra20-emc-table";
1294				clock-frequency = <300000>;
1295				nvidia,emc-registers = <0x00000012 0x00000027
1296					0x0000000d 0x00000006 0x00000007 0x00000005
1297					0x00000003 0x00000009 0x00000006 0x00000006
1298					0x00000003 0x00000003 0x00000002 0x00000006
1299					0x00000003 0x00000009 0x0000000c 0x0000045f
1300					0x00000000 0x00000004 0x00000004 0x00000006
1301					0x00000008 0x00000001 0x0000000e 0x0000002a
1302					0x00000003 0x0000000f 0x00000007 0x00000005
1303					0x00000002 0x000004e1 0x00000005 0x00000002
1304					0x00000000 0x00000000 0x00000282 0xe059048b
1305					0x007e0010 0x00000000 0x00000000 0x0000001b
1306					0x00000000 0x00000000 0x00000000 0x00000000>;
1307			};
1308		};
1309
1310		emc-tables@2 {
1311			nvidia,ram-code = <2>; /* hynix-8gb */
1312			reg = <2>;
1313
1314			#address-cells = <1>;
1315			#size-cells = <0>;
1316
1317			emc-table@25000 {
1318				reg = <25000>;
1319				compatible = "nvidia,tegra20-emc-table";
1320				clock-frequency = <25000>;
1321				nvidia,emc-registers = <0x00000002 0x00000006
1322					0x00000003 0x00000003 0x00000006 0x00000004
1323					0x00000002 0x00000009 0x00000003 0x00000003
1324					0x00000002 0x00000002 0x00000002 0x00000004
1325					0x00000003 0x00000008 0x0000000b 0x0000004d
1326					0x00000000 0x00000003 0x00000003 0x00000003
1327					0x00000008 0x00000001 0x0000000a 0x00000004
1328					0x00000003 0x00000008 0x00000004 0x00000006
1329					0x00000002 0x00000068 0x00000000 0x00000003
1330					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1331					0x00070000 0x00000000 0x00000000 0x00000003
1332					0x00000000 0x00000000 0x00000000 0x00000000>;
1333			};
1334
1335			emc-table@50000 {
1336				reg = <50000>;
1337				compatible = "nvidia,tegra20-emc-table";
1338				clock-frequency = <50000>;
1339				nvidia,emc-registers = <0x00000003 0x00000007
1340					0x00000003 0x00000003 0x00000006 0x00000004
1341					0x00000002 0x00000009 0x00000003 0x00000003
1342					0x00000002 0x00000002 0x00000002 0x00000005
1343					0x00000003 0x00000008 0x0000000b 0x0000009f
1344					0x00000000 0x00000003 0x00000003 0x00000003
1345					0x00000008 0x00000001 0x0000000a 0x00000007
1346					0x00000003 0x00000008 0x00000004 0x00000006
1347					0x00000002 0x000000d0 0x00000000 0x00000000
1348					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1349					0x00070000 0x00000000 0x00000000 0x00000005
1350					0x00000000 0x00000000 0x00000000 0x00000000>;
1351			};
1352
1353			emc-table@75000 {
1354				reg = <75000>;
1355				compatible = "nvidia,tegra20-emc-table";
1356				clock-frequency = <75000>;
1357				nvidia,emc-registers = <0x00000005 0x0000000a
1358					0x00000004 0x00000003 0x00000006 0x00000004
1359					0x00000002 0x00000009 0x00000003 0x00000003
1360					0x00000002 0x00000002 0x00000002 0x00000005
1361					0x00000003 0x00000008 0x0000000b 0x000000ff
1362					0x00000000 0x00000003 0x00000003 0x00000003
1363					0x00000008 0x00000001 0x0000000a 0x0000000b
1364					0x00000003 0x00000008 0x00000004 0x00000006
1365					0x00000002 0x00000138 0x00000000 0x00000000
1366					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1367					0x00070000 0x00000000 0x00000000 0x00000007
1368					0x00000000 0x00000000 0x00000000 0x00000000>;
1369			};
1370
1371			emc-table@150000 {
1372				reg = <150000>;
1373				compatible = "nvidia,tegra20-emc-table";
1374				clock-frequency = <150000>;
1375				nvidia,emc-registers = <0x00000009 0x00000014
1376					0x00000007 0x00000003 0x00000006 0x00000004
1377					0x00000002 0x00000009 0x00000003 0x00000003
1378					0x00000002 0x00000002 0x00000002 0x00000005
1379					0x00000003 0x00000008 0x0000000b 0x0000021f
1380					0x00000000 0x00000003 0x00000003 0x00000003
1381					0x00000008 0x00000001 0x0000000a 0x00000015
1382					0x00000003 0x00000008 0x00000004 0x00000006
1383					0x00000002 0x00000270 0x00000000 0x00000001
1384					0x00000000 0x00000000 0x00000282 0xa07c04ae
1385					0x007dd010 0x00000000 0x00000000 0x0000000e
1386					0x00000000 0x00000000 0x00000000 0x00000000>;
1387			};
1388
1389			emc-table@300000 {
1390				reg = <300000>;
1391				compatible = "nvidia,tegra20-emc-table";
1392				clock-frequency = <300000>;
1393				nvidia,emc-registers = <0x00000012 0x00000027
1394					0x0000000d 0x00000006 0x00000007 0x00000005
1395					0x00000003 0x00000009 0x00000006 0x00000006
1396					0x00000003 0x00000003 0x00000002 0x00000006
1397					0x00000003 0x00000009 0x0000000c 0x0000045f
1398					0x00000000 0x00000004 0x00000004 0x00000006
1399					0x00000008 0x00000001 0x0000000e 0x0000002a
1400					0x00000003 0x0000000f 0x00000007 0x00000005
1401					0x00000002 0x000004e1 0x00000005 0x00000002
1402					0x00000000 0x00000000 0x00000282 0xe059048b
1403					0x007e2010 0x00000000 0x00000000 0x0000001b
1404					0x00000000 0x00000000 0x00000000 0x00000000>;
1405			};
1406		};
1407
1408		emc-tables@3 {
1409			nvidia,ram-code = <3>; /* hynix-4gb */
1410			reg = <3>;
1411
1412			#address-cells = <1>;
1413			#size-cells = <0>;
1414
1415			emc-table@25000 {
1416				reg = <25000>;
1417				compatible = "nvidia,tegra20-emc-table";
1418				clock-frequency = <25000>;
1419				nvidia,emc-registers = <0x00000002 0x00000006
1420					0x00000003 0x00000003 0x00000006 0x00000004
1421					0x00000002 0x00000009 0x00000003 0x00000003
1422					0x00000002 0x00000002 0x00000002 0x00000004
1423					0x00000003 0x00000008 0x0000000b 0x0000004d
1424					0x00000000 0x00000003 0x00000003 0x00000003
1425					0x00000008 0x00000001 0x0000000a 0x00000004
1426					0x00000003 0x00000008 0x00000004 0x00000006
1427					0x00000002 0x00000068 0x00000000 0x00000003
1428					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1429					0x0007c000 0x00000000 0x00000000 0x00000003
1430					0x00000000 0x00000000 0x00000000 0x00000000>;
1431			};
1432
1433			emc-table@50000 {
1434				reg = <50000>;
1435				compatible = "nvidia,tegra20-emc-table";
1436				clock-frequency = <50000>;
1437				nvidia,emc-registers = <0x00000003 0x00000007
1438					0x00000003 0x00000003 0x00000006 0x00000004
1439					0x00000002 0x00000009 0x00000003 0x00000003
1440					0x00000002 0x00000002 0x00000002 0x00000005
1441					0x00000003 0x00000008 0x0000000b 0x0000009f
1442					0x00000000 0x00000003 0x00000003 0x00000003
1443					0x00000008 0x00000001 0x0000000a 0x00000007
1444					0x00000003 0x00000008 0x00000004 0x00000006
1445					0x00000002 0x000000d0 0x00000000 0x00000000
1446					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1447					0x0007c000 0x00078000 0x00000000 0x00000005
1448					0x00000000 0x00000000 0x00000000 0x00000000>;
1449			};
1450
1451			emc-table@75000 {
1452				reg = <75000>;
1453				compatible = "nvidia,tegra20-emc-table";
1454				clock-frequency = <75000>;
1455				nvidia,emc-registers = <0x00000005 0x0000000a
1456					0x00000004 0x00000003 0x00000006 0x00000004
1457					0x00000002 0x00000009 0x00000003 0x00000003
1458					0x00000002 0x00000002 0x00000002 0x00000005
1459					0x00000003 0x00000008 0x0000000b 0x000000ff
1460					0x00000000 0x00000003 0x00000003 0x00000003
1461					0x00000008 0x00000001 0x0000000a 0x0000000b
1462					0x00000003 0x00000008 0x00000004 0x00000006
1463					0x00000002 0x00000138 0x00000000 0x00000000
1464					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1465					0x0007c000 0x00000000 0x00000000 0x00000007
1466					0x00000000 0x00000000 0x00000000 0x00000000>;
1467			};
1468
1469			emc-table@150000 {
1470				reg = <150000>;
1471				compatible = "nvidia,tegra20-emc-table";
1472				clock-frequency = <150000>;
1473				nvidia,emc-registers = <0x00000009 0x00000014
1474					0x00000007 0x00000003 0x00000006 0x00000004
1475					0x00000002 0x00000009 0x00000003 0x00000003
1476					0x00000002 0x00000002 0x00000002 0x00000005
1477					0x00000003 0x00000008 0x0000000b 0x0000021f
1478					0x00000000 0x00000003 0x00000003 0x00000003
1479					0x00000008 0x00000001 0x0000000a 0x00000015
1480					0x00000003 0x00000008 0x00000004 0x00000006
1481					0x00000002 0x00000270 0x00000000 0x00000001
1482					0x00000000 0x00000000 0x00000282 0xa07c04ae
1483					0x007e4010 0x00000000 0x00000000 0x0000000e
1484					0x00000000 0x00000000 0x00000000 0x00000000>;
1485			};
1486
1487			emc-table@300000 {
1488				reg = <300000>;
1489				compatible = "nvidia,tegra20-emc-table";
1490				clock-frequency = <300000>;
1491				nvidia,emc-registers = <0x00000012 0x00000027
1492					0x0000000d 0x00000006 0x00000007 0x00000005
1493					0x00000003 0x00000009 0x00000006 0x00000006
1494					0x00000003 0x00000003 0x00000002 0x00000006
1495					0x00000003 0x00000009 0x0000000c 0x0000045f
1496					0x00000000 0x00000004 0x00000004 0x00000006
1497					0x00000008 0x00000001 0x0000000e 0x0000002a
1498					0x00000003 0x0000000f 0x00000007 0x00000005
1499					0x00000002 0x000004e1 0x00000005 0x00000002
1500					0x00000000 0x00000000 0x00000282 0xe059048b
1501					0x007e0010 0x00000000 0x00000000 0x0000001b
1502					0x00000000 0x00000000 0x00000000 0x00000000>;
1503			};
1504		};
1505	};
1506};
1507
1508&emc_icc_dvfs_opp_table {
1509	/delete-node/ opp@666000000;
1510	/delete-node/ opp@760000000;
1511};
1512