1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/input/gpio-keys.h> 4#include <dt-bindings/input/input.h> 5#include <dt-bindings/power/summit,smb347-charger.h> 6#include <dt-bindings/thermal/thermal.h> 7 8#include "tegra30.dtsi" 9#include "tegra30-cpu-opp.dtsi" 10#include "tegra30-cpu-opp-microvolt.dtsi" 11 12/ { 13 aliases { 14 mmc0 = &sdmmc4; /* eMMC */ 15 mmc1 = &sdmmc3; /* WiFi */ 16 17 rtc0 = &pmic; 18 rtc1 = "/rtc@7000e000"; 19 20 serial1 = &uartc; /* Bluetooth */ 21 serial2 = &uartb; /* GPS */ 22 }; 23 24 /* 25 * The decompressor and also some bootloaders rely on a 26 * pre-existing /chosen node to be available to insert the 27 * command line and merge other ATAGS info. 28 */ 29 chosen {}; 30 31 memory@80000000 { 32 reg = <0x80000000 0x40000000>; 33 }; 34 35 reserved-memory { 36 #address-cells = <1>; 37 #size-cells = <1>; 38 ranges; 39 40 linux,cma@80000000 { 41 compatible = "shared-dma-pool"; 42 alloc-ranges = <0x80000000 0x30000000>; 43 size = <0x10000000>; /* 256MiB */ 44 linux,cma-default; 45 reusable; 46 }; 47 48 ramoops@bfdf0000 { 49 compatible = "ramoops"; 50 reg = <0xbfdf0000 0x10000>; /* 64kB */ 51 console-size = <0x8000>; /* 32kB */ 52 record-size = <0x400>; /* 1kB */ 53 ecc-size = <16>; 54 }; 55 56 trustzone@bfe00000 { 57 reg = <0xbfe00000 0x200000>; 58 no-map; 59 }; 60 }; 61 62 host1x@50000000 { 63 dc@54200000 { 64 rgb { 65 status = "okay"; 66 67 port@0 { 68 lcd_output: endpoint { 69 remote-endpoint = <&lvds_encoder_input>; 70 bus-width = <24>; 71 }; 72 }; 73 }; 74 }; 75 }; 76 77 gpio@6000d000 { 78 init-mode-hog { 79 gpio-hog; 80 gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, 81 <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>, 82 <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 83 output-low; 84 }; 85 86 init-low-power-mode-hog { 87 gpio-hog; 88 gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 89 input; 90 }; 91 }; 92 93 pinmux@70000868 { 94 pinctrl-names = "default"; 95 pinctrl-0 = <&state_default>; 96 97 state_default: pinmux { 98 clk_32k_out_pa0 { 99 nvidia,pins = "clk_32k_out_pa0"; 100 nvidia,function = "blink"; 101 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 102 nvidia,tristate = <TEGRA_PIN_DISABLE>; 103 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 104 }; 105 uart3_cts_n_pa1 { 106 nvidia,pins = "uart3_cts_n_pa1", 107 "uart3_rxd_pw7"; 108 nvidia,function = "uartc"; 109 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 110 nvidia,tristate = <TEGRA_PIN_DISABLE>; 111 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 112 }; 113 dap2_fs_pa2 { 114 nvidia,pins = "dap2_fs_pa2", 115 "dap2_sclk_pa3", 116 "dap2_din_pa4", 117 "dap2_dout_pa5"; 118 nvidia,function = "i2s1"; 119 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 120 nvidia,tristate = <TEGRA_PIN_DISABLE>; 121 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 122 }; 123 sdmmc3_clk_pa6 { 124 nvidia,pins = "sdmmc3_clk_pa6"; 125 nvidia,function = "sdmmc3"; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127 nvidia,tristate = <TEGRA_PIN_DISABLE>; 128 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 129 }; 130 sdmmc3_cmd_pa7 { 131 nvidia,pins = "sdmmc3_cmd_pa7", 132 "sdmmc3_dat3_pb4", 133 "sdmmc3_dat2_pb5", 134 "sdmmc3_dat1_pb6", 135 "sdmmc3_dat0_pb7", 136 "sdmmc3_dat4_pd1", 137 "sdmmc3_dat6_pd3", 138 "sdmmc3_dat7_pd4"; 139 nvidia,function = "sdmmc3"; 140 nvidia,pull = <TEGRA_PIN_PULL_UP>; 141 nvidia,tristate = <TEGRA_PIN_DISABLE>; 142 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 143 }; 144 gmi_a17_pb0 { 145 nvidia,pins = "gmi_a17_pb0", 146 "gmi_a18_pb1"; 147 nvidia,function = "uartd"; 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 149 nvidia,tristate = <TEGRA_PIN_DISABLE>; 150 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 151 }; 152 lcd_pwr0_pb2 { 153 nvidia,pins = "lcd_pwr0_pb2", 154 "lcd_pwr1_pc1", 155 "lcd_m1_pw1"; 156 nvidia,function = "displaya"; 157 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 158 nvidia,tristate = <TEGRA_PIN_DISABLE>; 159 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 160 }; 161 lcd_pclk_pb3 { 162 nvidia,pins = "lcd_pclk_pb3", 163 "lcd_d0_pe0", 164 "lcd_d1_pe1", 165 "lcd_d2_pe2", 166 "lcd_d3_pe3", 167 "lcd_d4_pe4", 168 "lcd_d5_pe5", 169 "lcd_d6_pe6", 170 "lcd_d7_pe7", 171 "lcd_d8_pf0", 172 "lcd_d9_pf1", 173 "lcd_d10_pf2", 174 "lcd_d11_pf3", 175 "lcd_d12_pf4", 176 "lcd_d13_pf5", 177 "lcd_d14_pf6", 178 "lcd_d15_pf7", 179 "lcd_de_pj1", 180 "lcd_hsync_pj3", 181 "lcd_vsync_pj4", 182 "lcd_d16_pm0", 183 "lcd_d17_pm1", 184 "lcd_d18_pm2", 185 "lcd_d19_pm3", 186 "lcd_d20_pm4", 187 "lcd_d21_pm5", 188 "lcd_d22_pm6", 189 "lcd_d23_pm7", 190 "lcd_cs0_n_pn4", 191 "lcd_sdout_pn5", 192 "lcd_dc0_pn6", 193 "lcd_cs1_n_pw0", 194 "lcd_sdin_pz2", 195 "lcd_sck_pz4"; 196 nvidia,function = "displaya"; 197 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 198 nvidia,tristate = <TEGRA_PIN_DISABLE>; 199 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 200 }; 201 uart3_rts_n_pc0 { 202 nvidia,pins = "uart3_rts_n_pc0", 203 "uart3_txd_pw6"; 204 nvidia,function = "uartc"; 205 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 206 nvidia,tristate = <TEGRA_PIN_DISABLE>; 207 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 208 }; 209 uart2_txd_pc2 { 210 nvidia,pins = "uart2_txd_pc2", 211 "uart2_rts_n_pj6"; 212 nvidia,function = "uartb"; 213 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 214 nvidia,tristate = <TEGRA_PIN_DISABLE>; 215 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 216 }; 217 uart2_rxd_pc3 { 218 nvidia,pins = "uart2_rxd_pc3", 219 "uart2_cts_n_pj5"; 220 nvidia,function = "uartb"; 221 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 222 nvidia,tristate = <TEGRA_PIN_DISABLE>; 223 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 224 }; 225 gen1_i2c_scl_pc4 { 226 nvidia,pins = "gen1_i2c_scl_pc4", 227 "gen1_i2c_sda_pc5"; 228 nvidia,function = "i2c1"; 229 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 230 nvidia,tristate = <TEGRA_PIN_DISABLE>; 231 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 232 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 233 }; 234 gmi_wp_n_pc7 { 235 nvidia,pins = "gmi_wp_n_pc7", 236 "gmi_wait_pi7", 237 "gmi_cs4_n_pk2", 238 "gmi_cs3_n_pk4"; 239 nvidia,function = "rsvd1"; 240 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 241 nvidia,tristate = <TEGRA_PIN_ENABLE>; 242 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 243 }; 244 gmi_ad12_ph4 { 245 nvidia,pins = "gmi_ad12_ph4", 246 "gmi_cs0_n_pj0", 247 "gmi_cs1_n_pj2", 248 "gmi_cs2_n_pk3"; 249 nvidia,function = "rsvd1"; 250 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 251 nvidia,tristate = <TEGRA_PIN_ENABLE>; 252 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 253 }; 254 sdmmc3_dat5_pd0 { 255 nvidia,pins = "sdmmc3_dat5_pd0"; 256 nvidia,function = "sdmmc3"; 257 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 258 nvidia,tristate = <TEGRA_PIN_DISABLE>; 259 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 260 }; 261 gmi_ad0_pg0 { 262 nvidia,pins = "gmi_ad0_pg0", 263 "gmi_ad1_pg1", 264 "gmi_ad14_ph6", 265 "pu1"; 266 nvidia,function = "rsvd1"; 267 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 268 nvidia,tristate = <TEGRA_PIN_DISABLE>; 269 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 270 }; 271 gmi_ad2_pg2 { 272 nvidia,pins = "gmi_ad2_pg2", 273 "gmi_ad3_pg3", 274 "gmi_ad6_pg6", 275 "gmi_ad7_pg7"; 276 nvidia,function = "rsvd1"; 277 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 278 nvidia,tristate = <TEGRA_PIN_DISABLE>; 279 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 280 }; 281 gmi_ad4_pg4 { 282 nvidia,pins = "gmi_ad4_pg4", 283 "gmi_ad5_pg5"; 284 nvidia,function = "nand"; 285 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 286 nvidia,tristate = <TEGRA_PIN_DISABLE>; 287 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 288 }; 289 gmi_ad8_ph0 { 290 nvidia,pins = "gmi_ad8_ph0"; 291 nvidia,function = "pwm0"; 292 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 293 nvidia,tristate = <TEGRA_PIN_DISABLE>; 294 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 295 }; 296 gmi_ad9_ph1 { 297 nvidia,pins = "gmi_ad9_ph1"; 298 nvidia,function = "rsvd4"; 299 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 300 nvidia,tristate = <TEGRA_PIN_DISABLE>; 301 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 302 }; 303 gmi_ad10_ph2 { 304 nvidia,pins = "gmi_ad10_ph2"; 305 nvidia,function = "pwm2"; 306 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 307 nvidia,tristate = <TEGRA_PIN_ENABLE>; 308 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 309 }; 310 gmi_ad11_ph3 { 311 nvidia,pins = "gmi_ad11_ph3"; 312 nvidia,function = "pwm3"; 313 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 314 nvidia,tristate = <TEGRA_PIN_DISABLE>; 315 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 316 }; 317 gmi_ad13_ph5 { 318 nvidia,pins = "gmi_ad13_ph5", 319 "gmi_wr_n_pi0", 320 "gmi_oe_n_pi1", 321 "gmi_adv_n_pk0"; 322 nvidia,function = "rsvd1"; 323 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 324 nvidia,tristate = <TEGRA_PIN_ENABLE>; 325 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 326 }; 327 gmi_ad15_ph7 { 328 nvidia,pins = "gmi_ad15_ph7"; 329 nvidia,function = "rsvd1"; 330 nvidia,pull = <TEGRA_PIN_PULL_UP>; 331 nvidia,tristate = <TEGRA_PIN_DISABLE>; 332 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 333 }; 334 gmi_dqs_pi2 { 335 nvidia,pins = "gmi_dqs_pi2", 336 "pu2", 337 "pv1"; 338 nvidia,function = "rsvd1"; 339 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 340 nvidia,tristate = <TEGRA_PIN_DISABLE>; 341 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 342 }; 343 gmi_rst_n_pi4 { 344 nvidia,pins = "gmi_rst_n_pi4"; 345 nvidia,function = "nand"; 346 nvidia,pull = <TEGRA_PIN_PULL_UP>; 347 nvidia,tristate = <TEGRA_PIN_DISABLE>; 348 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 349 }; 350 gmi_iordy_pi5 { 351 nvidia,pins = "gmi_iordy_pi5"; 352 nvidia,function = "rsvd1"; 353 nvidia,pull = <TEGRA_PIN_PULL_UP>; 354 nvidia,tristate = <TEGRA_PIN_DISABLE>; 355 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 356 }; 357 gmi_cs7_n_pi6 { 358 nvidia,pins = "gmi_cs7_n_pi6", 359 "gmi_clk_pk1"; 360 nvidia,function = "nand"; 361 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 362 nvidia,tristate = <TEGRA_PIN_ENABLE>; 363 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 364 }; 365 gmi_a16_pj7 { 366 nvidia,pins = "gmi_a16_pj7", 367 "gmi_a19_pk7"; 368 nvidia,function = "uartd"; 369 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 370 nvidia,tristate = <TEGRA_PIN_DISABLE>; 371 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 372 }; 373 spdif_out_pk5 { 374 nvidia,pins = "spdif_out_pk5"; 375 nvidia,function = "spdif"; 376 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 377 nvidia,tristate = <TEGRA_PIN_DISABLE>; 378 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 379 }; 380 spdif_in_pk6 { 381 nvidia,pins = "spdif_in_pk6"; 382 nvidia,function = "spdif"; 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384 nvidia,tristate = <TEGRA_PIN_DISABLE>; 385 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 386 }; 387 dap1_fs_pn0 { 388 nvidia,pins = "dap1_fs_pn0", 389 "dap1_din_pn1", 390 "dap1_dout_pn2", 391 "dap1_sclk_pn3"; 392 nvidia,function = "i2s0"; 393 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 394 nvidia,tristate = <TEGRA_PIN_DISABLE>; 395 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 396 }; 397 hdmi_int_pn7 { 398 nvidia,pins = "hdmi_int_pn7"; 399 nvidia,function = "hdmi"; 400 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 401 nvidia,tristate = <TEGRA_PIN_ENABLE>; 402 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 403 }; 404 ulpi_data7_po0 { 405 nvidia,pins = "ulpi_data7_po0"; 406 nvidia,function = "uarta"; 407 nvidia,pull = <TEGRA_PIN_PULL_UP>; 408 nvidia,tristate = <TEGRA_PIN_ENABLE>; 409 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 410 }; 411 ulpi_data3_po4 { 412 nvidia,pins = "ulpi_data3_po4"; 413 nvidia,function = "ulpi"; 414 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 415 nvidia,tristate = <TEGRA_PIN_DISABLE>; 416 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 417 }; 418 dap3_fs_pp0 { 419 nvidia,pins = "dap3_fs_pp0"; 420 nvidia,function = "i2s2"; 421 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 422 nvidia,tristate = <TEGRA_PIN_DISABLE>; 423 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 424 }; 425 dap4_fs_pp4 { 426 nvidia,pins = "dap4_fs_pp4", 427 "dap4_din_pp5", 428 "dap4_dout_pp6", 429 "dap4_sclk_pp7"; 430 nvidia,function = "i2s3"; 431 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 432 nvidia,tristate = <TEGRA_PIN_DISABLE>; 433 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 434 }; 435 kb_col0_pq0 { 436 nvidia,pins = "kb_col0_pq0", 437 "kb_col1_pq1", 438 "kb_row1_pr1"; 439 nvidia,function = "kbc"; 440 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 441 nvidia,tristate = <TEGRA_PIN_ENABLE>; 442 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 443 }; 444 kb_col2_pq2 { 445 nvidia,pins = "kb_col2_pq2", 446 "kb_col3_pq3"; 447 nvidia,function = "rsvd4"; 448 nvidia,pull = <TEGRA_PIN_PULL_UP>; 449 nvidia,tristate = <TEGRA_PIN_ENABLE>; 450 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 451 }; 452 kb_col4_pq4 { 453 nvidia,pins = "kb_col4_pq4", 454 "kb_col5_pq5", 455 "kb_col7_pq7", 456 "kb_row2_pr2", 457 "kb_row4_pr4", 458 "kb_row5_pr5", 459 "kb_row14_ps6"; 460 nvidia,function = "kbc"; 461 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 462 nvidia,tristate = <TEGRA_PIN_ENABLE>; 463 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 464 }; 465 kb_row0_pr0 { 466 nvidia,pins = "kb_row0_pr0"; 467 nvidia,function = "rsvd4"; 468 nvidia,pull = <TEGRA_PIN_PULL_UP>; 469 nvidia,tristate = <TEGRA_PIN_DISABLE>; 470 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 471 }; 472 kb_row6_pr6 { 473 nvidia,pins = "kb_row6_pr6", 474 "kb_row8_ps0", 475 "kb_row9_ps1", 476 "kb_row10_ps2"; 477 nvidia,function = "kbc"; 478 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 479 nvidia,tristate = <TEGRA_PIN_DISABLE>; 480 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 481 }; 482 kb_row11_ps3 { 483 nvidia,pins = "kb_row11_ps3", 484 "kb_row12_ps4"; 485 nvidia,function = "kbc"; 486 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 487 nvidia,tristate = <TEGRA_PIN_DISABLE>; 488 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 489 }; 490 gen2_i2c_scl_pt5 { 491 nvidia,pins = "gen2_i2c_scl_pt5", 492 "gen2_i2c_sda_pt6"; 493 nvidia,function = "i2c2"; 494 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 495 nvidia,tristate = <TEGRA_PIN_DISABLE>; 496 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 497 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 498 }; 499 sdmmc4_cmd_pt7 { 500 nvidia,pins = "sdmmc4_cmd_pt7", 501 "sdmmc4_dat0_paa0", 502 "sdmmc4_dat1_paa1", 503 "sdmmc4_dat2_paa2", 504 "sdmmc4_dat3_paa3", 505 "sdmmc4_dat4_paa4", 506 "sdmmc4_dat5_paa5", 507 "sdmmc4_dat6_paa6", 508 "sdmmc4_dat7_paa7"; 509 nvidia,function = "sdmmc4"; 510 nvidia,pull = <TEGRA_PIN_PULL_UP>; 511 nvidia,tristate = <TEGRA_PIN_DISABLE>; 512 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 513 }; 514 pu0 { 515 nvidia,pins = "pu0", 516 "pu6"; 517 nvidia,function = "rsvd4"; 518 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 519 nvidia,tristate = <TEGRA_PIN_DISABLE>; 520 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 521 }; 522 jtag_rtck_pu7 { 523 nvidia,pins = "jtag_rtck_pu7"; 524 nvidia,function = "rtck"; 525 nvidia,pull = <TEGRA_PIN_PULL_UP>; 526 nvidia,tristate = <TEGRA_PIN_DISABLE>; 527 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 528 }; 529 pv0 { 530 nvidia,pins = "pv0"; 531 nvidia,function = "rsvd1"; 532 nvidia,pull = <TEGRA_PIN_PULL_UP>; 533 nvidia,tristate = <TEGRA_PIN_ENABLE>; 534 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 535 }; 536 ddc_scl_pv4 { 537 nvidia,pins = "ddc_scl_pv4", 538 "ddc_sda_pv5"; 539 nvidia,function = "i2c4"; 540 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 541 nvidia,tristate = <TEGRA_PIN_DISABLE>; 542 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 543 }; 544 crt_hsync_pv6 { 545 nvidia,pins = "crt_hsync_pv6", 546 "crt_vsync_pv7"; 547 nvidia,function = "crt"; 548 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 549 nvidia,tristate = <TEGRA_PIN_DISABLE>; 550 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 551 }; 552 spi2_cs1_n_pw2 { 553 nvidia,pins = "spi2_cs1_n_pw2", 554 "spi2_miso_px1", 555 "spi2_sck_px2"; 556 nvidia,function = "spi2"; 557 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 558 nvidia,tristate = <TEGRA_PIN_DISABLE>; 559 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 560 }; 561 clk1_out_pw4 { 562 nvidia,pins = "clk1_out_pw4"; 563 nvidia,function = "extperiph1"; 564 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 565 nvidia,tristate = <TEGRA_PIN_DISABLE>; 566 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 567 }; 568 clk2_out_pw5 { 569 nvidia,pins = "clk2_out_pw5"; 570 nvidia,function = "extperiph2"; 571 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 572 nvidia,tristate = <TEGRA_PIN_DISABLE>; 573 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 574 }; 575 spi2_cs0_n_px3 { 576 nvidia,pins = "spi2_cs0_n_px3"; 577 nvidia,function = "spi6"; 578 nvidia,pull = <TEGRA_PIN_PULL_UP>; 579 nvidia,tristate = <TEGRA_PIN_DISABLE>; 580 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 581 }; 582 spi1_mosi_px4 { 583 nvidia,pins = "spi1_mosi_px4", 584 "spi1_cs0_n_px6"; 585 nvidia,function = "spi1"; 586 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 587 nvidia,tristate = <TEGRA_PIN_DISABLE>; 588 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 589 }; 590 ulpi_clk_py0 { 591 nvidia,pins = "ulpi_clk_py0", 592 "ulpi_dir_py1"; 593 nvidia,function = "ulpi"; 594 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 595 nvidia,tristate = <TEGRA_PIN_ENABLE>; 596 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 597 }; 598 sdmmc1_dat3_py4 { 599 nvidia,pins = "sdmmc1_dat3_py4", 600 "sdmmc1_dat2_py5", 601 "sdmmc1_dat1_py6", 602 "sdmmc1_dat0_py7", 603 "sdmmc1_cmd_pz1"; 604 nvidia,function = "sdmmc1"; 605 nvidia,pull = <TEGRA_PIN_PULL_UP>; 606 nvidia,tristate = <TEGRA_PIN_DISABLE>; 607 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 608 }; 609 sdmmc1_clk_pz0 { 610 nvidia,pins = "sdmmc1_clk_pz0"; 611 nvidia,function = "sdmmc1"; 612 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613 nvidia,tristate = <TEGRA_PIN_DISABLE>; 614 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 615 }; 616 lcd_wr_n_pz3 { 617 nvidia,pins = "lcd_wr_n_pz3"; 618 nvidia,function = "displaya"; 619 nvidia,pull = <TEGRA_PIN_PULL_UP>; 620 nvidia,tristate = <TEGRA_PIN_DISABLE>; 621 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 622 }; 623 sys_clk_req_pz5 { 624 nvidia,pins = "sys_clk_req_pz5"; 625 nvidia,function = "sysclk"; 626 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 627 nvidia,tristate = <TEGRA_PIN_DISABLE>; 628 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 629 }; 630 pwr_i2c_scl_pz6 { 631 nvidia,pins = "pwr_i2c_scl_pz6", 632 "pwr_i2c_sda_pz7"; 633 nvidia,function = "i2cpwr"; 634 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 635 nvidia,tristate = <TEGRA_PIN_DISABLE>; 636 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 637 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 638 }; 639 pbb0 { 640 nvidia,pins = "pbb0", 641 "pcc1"; 642 nvidia,function = "rsvd2"; 643 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 644 nvidia,tristate = <TEGRA_PIN_DISABLE>; 645 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 646 }; 647 cam_i2c_scl_pbb1 { 648 nvidia,pins = "cam_i2c_scl_pbb1", 649 "cam_i2c_sda_pbb2"; 650 nvidia,function = "i2c3"; 651 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 652 nvidia,tristate = <TEGRA_PIN_DISABLE>; 653 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 654 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 655 }; 656 pbb3 { 657 nvidia,pins = "pbb3"; 658 nvidia,function = "vgp3"; 659 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 660 nvidia,tristate = <TEGRA_PIN_DISABLE>; 661 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 662 }; 663 pbb4 { 664 nvidia,pins = "pbb4"; 665 nvidia,function = "vgp4"; 666 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 667 nvidia,tristate = <TEGRA_PIN_DISABLE>; 668 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 669 }; 670 pbb5 { 671 nvidia,pins = "pbb5"; 672 nvidia,function = "vgp5"; 673 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 674 nvidia,tristate = <TEGRA_PIN_DISABLE>; 675 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 676 }; 677 pbb6 { 678 nvidia,pins = "pbb6"; 679 nvidia,function = "vgp6"; 680 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 681 nvidia,tristate = <TEGRA_PIN_DISABLE>; 682 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 683 }; 684 pbb7 { 685 nvidia,pins = "pbb7", 686 "pcc2"; 687 nvidia,function = "i2s4"; 688 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 689 nvidia,tristate = <TEGRA_PIN_DISABLE>; 690 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 691 }; 692 cam_mclk_pcc0 { 693 nvidia,pins = "cam_mclk_pcc0"; 694 nvidia,function = "vi_alt3"; 695 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 696 nvidia,tristate = <TEGRA_PIN_DISABLE>; 697 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 698 }; 699 sdmmc4_rst_n_pcc3 { 700 nvidia,pins = "sdmmc4_rst_n_pcc3"; 701 nvidia,function = "rsvd2"; 702 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 703 nvidia,tristate = <TEGRA_PIN_DISABLE>; 704 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 705 }; 706 sdmmc4_clk_pcc4 { 707 nvidia,pins = "sdmmc4_clk_pcc4"; 708 nvidia,function = "sdmmc4"; 709 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 710 nvidia,tristate = <TEGRA_PIN_DISABLE>; 711 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 712 }; 713 clk2_req_pcc5 { 714 nvidia,pins = "clk2_req_pcc5"; 715 nvidia,function = "dap"; 716 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 717 nvidia,tristate = <TEGRA_PIN_DISABLE>; 718 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 719 }; 720 pex_l2_rst_n_pcc6 { 721 nvidia,pins = "pex_l2_rst_n_pcc6", 722 "pex_l2_clkreq_n_pcc7"; 723 nvidia,function = "pcie"; 724 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 725 nvidia,tristate = <TEGRA_PIN_DISABLE>; 726 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 727 }; 728 pex_wake_n_pdd3 { 729 nvidia,pins = "pex_wake_n_pdd3", 730 "pex_l2_prsnt_n_pdd7"; 731 nvidia,function = "pcie"; 732 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 733 nvidia,tristate = <TEGRA_PIN_DISABLE>; 734 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 735 }; 736 clk3_out_pee0 { 737 nvidia,pins = "clk3_out_pee0"; 738 nvidia,function = "extperiph3"; 739 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 740 nvidia,tristate = <TEGRA_PIN_DISABLE>; 741 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 742 }; 743 clk1_req_pee2 { 744 nvidia,pins = "clk1_req_pee2"; 745 nvidia,function = "dap"; 746 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 747 nvidia,tristate = <TEGRA_PIN_ENABLE>; 748 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 749 }; 750 hdmi_cec_pee3 { 751 nvidia,pins = "hdmi_cec_pee3"; 752 nvidia,function = "cec"; 753 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 754 nvidia,tristate = <TEGRA_PIN_DISABLE>; 755 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 756 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 757 }; 758 owr { 759 nvidia,pins = "owr"; 760 nvidia,function = "owr"; 761 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 762 nvidia,tristate = <TEGRA_PIN_DISABLE>; 763 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 764 }; 765 drive_dap1 { 766 nvidia,pins = "drive_dap1", 767 "drive_dap2", 768 "drive_dbg", 769 "drive_at5", 770 "drive_gme", 771 "drive_ddc", 772 "drive_ao1", 773 "drive_uart3"; 774 nvidia,high-speed-mode = <0>; 775 nvidia,schmitt = <TEGRA_PIN_ENABLE>; 776 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 777 nvidia,pull-down-strength = <31>; 778 nvidia,pull-up-strength = <31>; 779 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 780 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 781 }; 782 drive_sdio1 { 783 nvidia,pins = "drive_sdio1", 784 "drive_sdio3"; 785 nvidia,high-speed-mode = <0>; 786 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 787 nvidia,pull-down-strength = <46>; 788 nvidia,pull-up-strength = <42>; 789 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 790 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 791 }; 792 drive_gma { 793 nvidia,pins = "drive_gma", 794 "drive_gmb", 795 "drive_gmc", 796 "drive_gmd"; 797 nvidia,pull-down-strength = <9>; 798 nvidia,pull-up-strength = <9>; 799 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 800 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 801 }; 802 }; 803 }; 804 805 uartb: serial@70006040 { 806 compatible = "nvidia,tegra30-hsuart"; 807 /* GPS BCM4751 */ 808 }; 809 810 uartc: serial@70006200 { 811 compatible = "nvidia,tegra30-hsuart"; 812 status = "okay"; 813 814 nvidia,adjust-baud-rates = <0 9600 100>, 815 <9600 115200 200>, 816 <1000000 4000000 136>; 817 818 /* Azurewave AW-NH665 BCM4330B1 */ 819 bluetooth { 820 compatible = "brcm,bcm4330-bt"; 821 822 interrupt-parent = <&gpio>; 823 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 824 interrupt-names = "host-wakeup"; 825 826 max-speed = <4000000>; 827 828 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 829 clock-names = "txco"; 830 831 vbat-supply = <&vdd_3v3_sys>; 832 vddio-supply = <&vdd_1v8>; 833 834 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 835 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 836 }; 837 }; 838 839 pwm: pwm@7000a000 { 840 status = "okay"; 841 }; 842 843 i2c@7000c400 { 844 clock-frequency = <400000>; 845 status = "okay"; 846 847 touchscreen@10 { 848 compatible ="elan,ektf3624"; 849 reg = <0x10>; 850 851 interrupt-parent = <&gpio>; 852 interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>; 853 854 reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; 855 856 vcc33-supply = <&vcc_3v3_ts>; 857 vccio-supply = <&vcc_3v3_ts>; 858 859 touchscreen-size-x = <2112>; 860 touchscreen-size-y = <1280>; 861 touchscreen-swapped-x-y; 862 touchscreen-inverted-x; 863 }; 864 }; 865 866 i2c@7000c500 { 867 clock-frequency = <100000>; 868 status = "okay"; 869 870 compass@e { 871 compatible = "asahi-kasei,ak8974"; 872 reg = <0x0e>; 873 874 interrupt-parent = <&gpio>; 875 interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>; 876 877 avdd-supply = <&vdd_3v3_sys>; 878 dvdd-supply = <&vdd_1v8>; 879 880 mount-matrix = "0", "-1", "0", 881 "-1", "0", "0", 882 "0", "0", "-1"; 883 }; 884 885 light-sensor@1c { 886 compatible = "dynaimage,al3010"; 887 reg = <0x1c>; 888 889 interrupt-parent = <&gpio>; 890 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 891 892 vdd-supply = <&vdd_3v3_sys>; 893 }; 894 895 accelerometer@68 { 896 compatible = "invensense,mpu6050"; 897 reg = <0x68>; 898 899 interrupt-parent = <&gpio>; 900 interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>; 901 902 vdd-supply = <&vdd_3v3_sys>; 903 vddio-supply = <&vdd_1v8>; 904 905 mount-matrix = "0", "-1", "0", 906 "-1", "0", "0", 907 "0", "0", "-1"; 908 }; 909 }; 910 911 i2c@7000d000 { 912 clock-frequency = <100000>; 913 status = "okay"; 914 915 rt5640: audio-codec@1c { 916 compatible = "realtek,rt5640"; 917 reg = <0x1c>; 918 919 realtek,dmic1-data-pin = <1>; 920 }; 921 922 nct72: temperature-sensor@4c { 923 compatible = "onnn,nct1008"; 924 reg = <0x4c>; 925 vcc-supply = <&vdd_3v3_sys>; 926 927 interrupt-parent = <&gpio>; 928 interrupts = <TEGRA_GPIO(S, 3) IRQ_TYPE_EDGE_FALLING>; 929 930 #thermal-sensor-cells = <1>; 931 }; 932 933 fuel-gauge@55 { 934 compatible = "ti,bq27541"; 935 reg = <0x55>; 936 power-supplies = <&power_supply>; 937 }; 938 939 power_supply: charger@6a { 940 compatible = "summit,smb347"; 941 reg = <0x6a>; 942 943 interrupt-parent = <&gpio>; 944 interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>; 945 946 summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>; 947 summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>; 948 summit,enable-usb-charging; 949 950 monitored-battery = <&battery_cell>; 951 952 usb_vbus: usb-vbus { 953 regulator-name = "usb_vbus"; 954 regulator-min-microvolt = <5000000>; 955 regulator-max-microvolt = <5000000>; 956 regulator-min-microamp = <750000>; 957 regulator-max-microamp = <750000>; 958 959 /* 960 * SMB347 INOK input pin is connected to PMIC's 961 * ACOK output, which is fixed to ACTIVE_LOW as 962 * long as battery voltage is in a good range. 963 * 964 * Active INOK disables SMB347 output, so polarity 965 * needs to be toggled when we want to get the 966 * output. 967 */ 968 summit,needs-inok-toggle; 969 }; 970 }; 971 }; 972 973 pmc@7000e400 { 974 status = "okay"; 975 nvidia,invert-interrupt; 976 nvidia,suspend-mode = <1>; 977 nvidia,cpu-pwr-good-time = <2000>; 978 nvidia,cpu-pwr-off-time = <200>; 979 nvidia,core-pwr-good-time = <3845 3845>; 980 nvidia,core-pwr-off-time = <0>; 981 nvidia,core-power-req-active-high; 982 nvidia,sys-clock-req-active-high; 983 }; 984 985 ahub@70080000 { 986 i2s@70080400 { 987 status = "okay"; 988 }; 989 }; 990 991 brcm_wifi_pwrseq: wifi-pwrseq { 992 compatible = "mmc-pwrseq-simple"; 993 994 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 995 clock-names = "ext_clock"; 996 997 reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; 998 post-power-on-delay-ms = <300>; 999 power-off-delay-us = <300>; 1000 }; 1001 1002 sdmmc3: mmc@78000400 { 1003 status = "okay"; 1004 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 1008 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 1009 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; 1010 assigned-clock-rates = <50000000>; 1011 1012 max-frequency = <50000000>; 1013 keep-power-in-suspend; 1014 bus-width = <4>; 1015 non-removable; 1016 1017 mmc-pwrseq = <&brcm_wifi_pwrseq>; 1018 vmmc-supply = <&vdd_3v3_sys>; 1019 vqmmc-supply = <&vdd_1v8>; 1020 1021 /* Azurewave AW-NH665 BCM4330 */ 1022 wifi@1 { 1023 reg = <1>; 1024 compatible = "brcm,bcm4329-fmac"; 1025 interrupt-parent = <&gpio>; 1026 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>; 1027 interrupt-names = "host-wake"; 1028 }; 1029 }; 1030 1031 sdmmc4: mmc@78000600 { 1032 status = "okay"; 1033 bus-width = <8>; 1034 vmmc-supply = <&vcore_emmc>; 1035 vqmmc-supply = <&vdd_1v8>; 1036 non-removable; 1037 }; 1038 1039 usb@7d000000 { 1040 compatible = "nvidia,tegra30-udc"; 1041 status = "okay"; 1042 dr_mode = "otg"; 1043 vbus-supply = <&usb_vbus>; 1044 }; 1045 1046 usb-phy@7d000000 { 1047 status = "okay"; 1048 dr_mode = "otg"; 1049 nvidia,hssync-start-delay = <0>; 1050 nvidia,xcvr-lsfslew = <2>; 1051 nvidia,xcvr-lsrslew = <2>; 1052 }; 1053 1054 backlight: backlight { 1055 compatible = "pwm-backlight"; 1056 1057 power-supply = <&vdd_5v0_sys>; 1058 pwms = <&pwm 0 50000>; 1059 1060 brightness-levels = <1 255>; 1061 num-interpolated-steps = <254>; 1062 default-brightness-level = <15>; 1063 }; 1064 1065 battery_cell: battery-cell { 1066 compatible = "simple-battery"; 1067 constant-charge-current-max-microamp = <1800000>; 1068 operating-range-celsius = <0 45>; 1069 }; 1070 1071 /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1072 clk32k_in: clock@0 { 1073 compatible = "fixed-clock"; 1074 #clock-cells = <0>; 1075 clock-frequency = <32768>; 1076 clock-output-names = "pmic-oscillator"; 1077 }; 1078 1079 cpus { 1080 cpu0: cpu@0 { 1081 cpu-supply = <&vdd_cpu>; 1082 operating-points-v2 = <&cpu0_opp_table>; 1083 #cooling-cells = <2>; 1084 }; 1085 1086 cpu1: cpu@1 { 1087 cpu-supply = <&vdd_cpu>; 1088 operating-points-v2 = <&cpu0_opp_table>; 1089 #cooling-cells = <2>; 1090 }; 1091 1092 cpu2: cpu@2 { 1093 cpu-supply = <&vdd_cpu>; 1094 operating-points-v2 = <&cpu0_opp_table>; 1095 #cooling-cells = <2>; 1096 }; 1097 1098 cpu3: cpu@3 { 1099 cpu-supply = <&vdd_cpu>; 1100 operating-points-v2 = <&cpu0_opp_table>; 1101 #cooling-cells = <2>; 1102 }; 1103 }; 1104 1105 display-panel { 1106 /* 1107 * Nexus 7 supports two compatible panel models: 1108 * 1109 * 1. hydis,hv070wx2-1e0 1110 * 2. chunghwa,claa070wp03xg 1111 * 1112 * We want to use timing which is optimized for Nexus 7, 1113 * hence we need to customize the timing. 1114 */ 1115 compatible = "panel-lvds"; 1116 1117 power-supply = <&vdd_pnl>; 1118 backlight = <&backlight>; 1119 1120 width-mm = <94>; 1121 height-mm = <150>; 1122 rotation = <180>; 1123 1124 data-mapping = "jeida-24"; 1125 1126 port { 1127 panel_input: endpoint { 1128 remote-endpoint = <&lvds_encoder_output>; 1129 }; 1130 }; 1131 }; 1132 1133 firmware { 1134 trusted-foundations { 1135 compatible = "tlm,trusted-foundations"; 1136 tlm,version-major = <0x0>; 1137 tlm,version-minor = <0x0>; 1138 }; 1139 }; 1140 1141 gpio-keys { 1142 compatible = "gpio-keys"; 1143 1144 hall-sensor { 1145 label = "Lid"; 1146 gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; 1147 linux,input-type = <EV_SW>; 1148 linux,code = <SW_LID>; 1149 debounce-interval = <500>; 1150 wakeup-event-action = <EV_ACT_DEASSERTED>; 1151 wakeup-source; 1152 }; 1153 1154 power { 1155 label = "Power"; 1156 gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; 1157 linux,code = <KEY_POWER>; 1158 debounce-interval = <10>; 1159 wakeup-event-action = <EV_ACT_ASSERTED>; 1160 wakeup-source; 1161 }; 1162 1163 volume-up { 1164 label = "Volume Up"; 1165 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; 1166 linux,code = <KEY_VOLUMEUP>; 1167 debounce-interval = <10>; 1168 wakeup-event-action = <EV_ACT_ASSERTED>; 1169 wakeup-source; 1170 }; 1171 1172 volume-down { 1173 label = "Volume Down"; 1174 gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; 1175 linux,code = <KEY_VOLUMEDOWN>; 1176 debounce-interval = <10>; 1177 wakeup-event-action = <EV_ACT_ASSERTED>; 1178 wakeup-source; 1179 }; 1180 }; 1181 1182 lvds-encoder { 1183 compatible = "ti,sn75lvds83", "lvds-encoder"; 1184 1185 powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; 1186 power-supply = <&vdd_3v3_sys>; 1187 1188 ports { 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 1192 port@0 { 1193 reg = <0>; 1194 1195 lvds_encoder_input: endpoint { 1196 remote-endpoint = <&lcd_output>; 1197 }; 1198 }; 1199 1200 port@1 { 1201 reg = <1>; 1202 1203 lvds_encoder_output: endpoint { 1204 remote-endpoint = <&panel_input>; 1205 }; 1206 }; 1207 }; 1208 }; 1209 1210 vdd_5v0_sys: regulator@0 { 1211 compatible = "regulator-fixed"; 1212 regulator-name = "vdd_5v0"; 1213 regulator-min-microvolt = <5000000>; 1214 regulator-max-microvolt = <5000000>; 1215 regulator-always-on; 1216 regulator-boot-on; 1217 }; 1218 1219 vdd_3v3_sys: regulator@1 { 1220 compatible = "regulator-fixed"; 1221 regulator-name = "vdd_3v3"; 1222 regulator-min-microvolt = <3300000>; 1223 regulator-max-microvolt = <3300000>; 1224 regulator-always-on; 1225 regulator-boot-on; 1226 vin-supply = <&vdd_5v0_sys>; 1227 }; 1228 1229 vdd_pnl: regulator@2 { 1230 compatible = "regulator-fixed"; 1231 regulator-name = "vdd_panel"; 1232 regulator-min-microvolt = <3300000>; 1233 regulator-max-microvolt = <3300000>; 1234 regulator-enable-ramp-delay = <300000>; 1235 gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; 1236 enable-active-high; 1237 vin-supply = <&vdd_3v3_sys>; 1238 }; 1239 1240 vcc_3v3_ts: regulator@3 { 1241 compatible = "regulator-fixed"; 1242 regulator-name = "ldo_s-1167_3v3"; 1243 regulator-min-microvolt = <3300000>; 1244 regulator-max-microvolt = <3300000>; 1245 regulator-always-on; 1246 regulator-boot-on; 1247 vin-supply = <&vdd_5v0_sys>; 1248 }; 1249 1250 sound { 1251 compatible = "nvidia,tegra-audio-rt5640-grouper", 1252 "nvidia,tegra-audio-rt5640"; 1253 nvidia,model = "ASUS Google Nexus 7 ALC5642"; 1254 1255 nvidia,audio-routing = 1256 "Headphones", "HPOR", 1257 "Headphones", "HPOL", 1258 "Speakers", "SPORP", 1259 "Speakers", "SPORN", 1260 "Speakers", "SPOLP", 1261 "Speakers", "SPOLN", 1262 "DMIC1", "Mic Jack"; 1263 1264 nvidia,i2s-controller = <&tegra_i2s1>; 1265 nvidia,audio-codec = <&rt5640>; 1266 1267 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 1268 1269 clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 1270 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1271 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1272 clock-names = "pll_a", "pll_a_out0", "mclk"; 1273 1274 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 1275 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1276 1277 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1278 <&tegra_car TEGRA30_CLK_EXTERN1>; 1279 }; 1280 1281 thermal-zones { 1282 /* 1283 * NCT72 has two sensors: 1284 * 1285 * 0: internal that monitors ambient/skin temperature 1286 * 1: external that is connected to the CPU's diode 1287 * 1288 * Ideally we should use userspace thermal governor, 1289 * but it's a much more complex solution. The "skin" 1290 * zone is a simpler solution which prevents Nexus 7 1291 * from getting too hot from a user's tactile perspective. 1292 * The CPU zone is intended to protect silicon from damage. 1293 */ 1294 1295 skin-thermal { 1296 polling-delay-passive = <1000>; /* milliseconds */ 1297 polling-delay = <5000>; /* milliseconds */ 1298 1299 thermal-sensors = <&nct72 0>; 1300 1301 trips { 1302 trip0: skin-alert { 1303 /* throttle at 57C until temperature drops to 56.8C */ 1304 temperature = <57000>; 1305 hysteresis = <200>; 1306 type = "passive"; 1307 }; 1308 1309 trip1: skin-crit { 1310 /* shut down at 65C */ 1311 temperature = <65000>; 1312 hysteresis = <2000>; 1313 type = "critical"; 1314 }; 1315 }; 1316 1317 cooling-maps { 1318 map0 { 1319 trip = <&trip0>; 1320 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1321 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1322 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1323 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1324 <&actmon THERMAL_NO_LIMIT 1325 THERMAL_NO_LIMIT>; 1326 }; 1327 }; 1328 }; 1329 1330 cpu-thermal { 1331 polling-delay-passive = <1000>; /* milliseconds */ 1332 polling-delay = <5000>; /* milliseconds */ 1333 1334 thermal-sensors = <&nct72 1>; 1335 1336 trips { 1337 trip2: cpu-alert { 1338 /* throttle at 85C until temperature drops to 84.8C */ 1339 temperature = <85000>; 1340 hysteresis = <200>; 1341 type = "passive"; 1342 }; 1343 1344 trip3: cpu-crit { 1345 /* shut down at 90C */ 1346 temperature = <90000>; 1347 hysteresis = <2000>; 1348 type = "critical"; 1349 }; 1350 }; 1351 1352 cooling-maps { 1353 map1 { 1354 trip = <&trip2>; 1355 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1356 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1357 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1358 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1359 <&actmon THERMAL_NO_LIMIT 1360 THERMAL_NO_LIMIT>; 1361 }; 1362 }; 1363 }; 1364 }; 1365}; 1366