1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
4  *
5  * Copyright (C) 2021 Cirrus Logic, Inc. and
6  *                    Cirrus Logic International Semiconductor Ltd.
7  */
8 
9 #ifndef __CS8409_PATCH_H
10 #define __CS8409_PATCH_H
11 
12 #include <linux/pci.h>
13 #include <sound/tlv.h>
14 #include <linux/workqueue.h>
15 #include <sound/hda_codec.h>
16 #include "hda_local.h"
17 #include "hda_auto_parser.h"
18 #include "hda_jack.h"
19 #include "hda_generic.h"
20 
21 /* CS8409 Specific Definitions */
22 
23 enum cs8409_pins {
24 	CS8409_PIN_ROOT,
25 	CS8409_PIN_AFG,
26 	CS8409_PIN_ASP1_OUT_A,
27 	CS8409_PIN_ASP1_OUT_B,
28 	CS8409_PIN_ASP1_OUT_C,
29 	CS8409_PIN_ASP1_OUT_D,
30 	CS8409_PIN_ASP1_OUT_E,
31 	CS8409_PIN_ASP1_OUT_F,
32 	CS8409_PIN_ASP1_OUT_G,
33 	CS8409_PIN_ASP1_OUT_H,
34 	CS8409_PIN_ASP2_OUT_A,
35 	CS8409_PIN_ASP2_OUT_B,
36 	CS8409_PIN_ASP2_OUT_C,
37 	CS8409_PIN_ASP2_OUT_D,
38 	CS8409_PIN_ASP2_OUT_E,
39 	CS8409_PIN_ASP2_OUT_F,
40 	CS8409_PIN_ASP2_OUT_G,
41 	CS8409_PIN_ASP2_OUT_H,
42 	CS8409_PIN_ASP1_IN_A,
43 	CS8409_PIN_ASP1_IN_B,
44 	CS8409_PIN_ASP1_IN_C,
45 	CS8409_PIN_ASP1_IN_D,
46 	CS8409_PIN_ASP1_IN_E,
47 	CS8409_PIN_ASP1_IN_F,
48 	CS8409_PIN_ASP1_IN_G,
49 	CS8409_PIN_ASP1_IN_H,
50 	CS8409_PIN_ASP2_IN_A,
51 	CS8409_PIN_ASP2_IN_B,
52 	CS8409_PIN_ASP2_IN_C,
53 	CS8409_PIN_ASP2_IN_D,
54 	CS8409_PIN_ASP2_IN_E,
55 	CS8409_PIN_ASP2_IN_F,
56 	CS8409_PIN_ASP2_IN_G,
57 	CS8409_PIN_ASP2_IN_H,
58 	CS8409_PIN_DMIC1,
59 	CS8409_PIN_DMIC2,
60 	CS8409_PIN_ASP1_TRANSMITTER_A,
61 	CS8409_PIN_ASP1_TRANSMITTER_B,
62 	CS8409_PIN_ASP1_TRANSMITTER_C,
63 	CS8409_PIN_ASP1_TRANSMITTER_D,
64 	CS8409_PIN_ASP1_TRANSMITTER_E,
65 	CS8409_PIN_ASP1_TRANSMITTER_F,
66 	CS8409_PIN_ASP1_TRANSMITTER_G,
67 	CS8409_PIN_ASP1_TRANSMITTER_H,
68 	CS8409_PIN_ASP2_TRANSMITTER_A,
69 	CS8409_PIN_ASP2_TRANSMITTER_B,
70 	CS8409_PIN_ASP2_TRANSMITTER_C,
71 	CS8409_PIN_ASP2_TRANSMITTER_D,
72 	CS8409_PIN_ASP2_TRANSMITTER_E,
73 	CS8409_PIN_ASP2_TRANSMITTER_F,
74 	CS8409_PIN_ASP2_TRANSMITTER_G,
75 	CS8409_PIN_ASP2_TRANSMITTER_H,
76 	CS8409_PIN_ASP1_RECEIVER_A,
77 	CS8409_PIN_ASP1_RECEIVER_B,
78 	CS8409_PIN_ASP1_RECEIVER_C,
79 	CS8409_PIN_ASP1_RECEIVER_D,
80 	CS8409_PIN_ASP1_RECEIVER_E,
81 	CS8409_PIN_ASP1_RECEIVER_F,
82 	CS8409_PIN_ASP1_RECEIVER_G,
83 	CS8409_PIN_ASP1_RECEIVER_H,
84 	CS8409_PIN_ASP2_RECEIVER_A,
85 	CS8409_PIN_ASP2_RECEIVER_B,
86 	CS8409_PIN_ASP2_RECEIVER_C,
87 	CS8409_PIN_ASP2_RECEIVER_D,
88 	CS8409_PIN_ASP2_RECEIVER_E,
89 	CS8409_PIN_ASP2_RECEIVER_F,
90 	CS8409_PIN_ASP2_RECEIVER_G,
91 	CS8409_PIN_ASP2_RECEIVER_H,
92 	CS8409_PIN_DMIC1_IN,
93 	CS8409_PIN_DMIC2_IN,
94 	CS8409_PIN_BEEP_GEN,
95 	CS8409_PIN_VENDOR_WIDGET
96 };
97 
98 enum cs8409_coefficient_index_registers {
99 	CS8409_DEV_CFG1,
100 	CS8409_DEV_CFG2,
101 	CS8409_DEV_CFG3,
102 	CS8409_ASP1_CLK_CTRL1,
103 	CS8409_ASP1_CLK_CTRL2,
104 	CS8409_ASP1_CLK_CTRL3,
105 	CS8409_ASP2_CLK_CTRL1,
106 	CS8409_ASP2_CLK_CTRL2,
107 	CS8409_ASP2_CLK_CTRL3,
108 	CS8409_DMIC_CFG,
109 	CS8409_BEEP_CFG,
110 	ASP1_RX_NULL_INS_RMV,
111 	ASP1_Rx_RATE1,
112 	ASP1_Rx_RATE2,
113 	ASP1_Tx_NULL_INS_RMV,
114 	ASP1_Tx_RATE1,
115 	ASP1_Tx_RATE2,
116 	ASP2_Rx_NULL_INS_RMV,
117 	ASP2_Rx_RATE1,
118 	ASP2_Rx_RATE2,
119 	ASP2_Tx_NULL_INS_RMV,
120 	ASP2_Tx_RATE1,
121 	ASP2_Tx_RATE2,
122 	ASP1_SYNC_CTRL,
123 	ASP2_SYNC_CTRL,
124 	ASP1_A_TX_CTRL1,
125 	ASP1_A_TX_CTRL2,
126 	ASP1_B_TX_CTRL1,
127 	ASP1_B_TX_CTRL2,
128 	ASP1_C_TX_CTRL1,
129 	ASP1_C_TX_CTRL2,
130 	ASP1_D_TX_CTRL1,
131 	ASP1_D_TX_CTRL2,
132 	ASP1_E_TX_CTRL1,
133 	ASP1_E_TX_CTRL2,
134 	ASP1_F_TX_CTRL1,
135 	ASP1_F_TX_CTRL2,
136 	ASP1_G_TX_CTRL1,
137 	ASP1_G_TX_CTRL2,
138 	ASP1_H_TX_CTRL1,
139 	ASP1_H_TX_CTRL2,
140 	ASP2_A_TX_CTRL1,
141 	ASP2_A_TX_CTRL2,
142 	ASP2_B_TX_CTRL1,
143 	ASP2_B_TX_CTRL2,
144 	ASP2_C_TX_CTRL1,
145 	ASP2_C_TX_CTRL2,
146 	ASP2_D_TX_CTRL1,
147 	ASP2_D_TX_CTRL2,
148 	ASP2_E_TX_CTRL1,
149 	ASP2_E_TX_CTRL2,
150 	ASP2_F_TX_CTRL1,
151 	ASP2_F_TX_CTRL2,
152 	ASP2_G_TX_CTRL1,
153 	ASP2_G_TX_CTRL2,
154 	ASP2_H_TX_CTRL1,
155 	ASP2_H_TX_CTRL2,
156 	ASP1_A_RX_CTRL1,
157 	ASP1_A_RX_CTRL2,
158 	ASP1_B_RX_CTRL1,
159 	ASP1_B_RX_CTRL2,
160 	ASP1_C_RX_CTRL1,
161 	ASP1_C_RX_CTRL2,
162 	ASP1_D_RX_CTRL1,
163 	ASP1_D_RX_CTRL2,
164 	ASP1_E_RX_CTRL1,
165 	ASP1_E_RX_CTRL2,
166 	ASP1_F_RX_CTRL1,
167 	ASP1_F_RX_CTRL2,
168 	ASP1_G_RX_CTRL1,
169 	ASP1_G_RX_CTRL2,
170 	ASP1_H_RX_CTRL1,
171 	ASP1_H_RX_CTRL2,
172 	ASP2_A_RX_CTRL1,
173 	ASP2_A_RX_CTRL2,
174 	ASP2_B_RX_CTRL1,
175 	ASP2_B_RX_CTRL2,
176 	ASP2_C_RX_CTRL1,
177 	ASP2_C_RX_CTRL2,
178 	ASP2_D_RX_CTRL1,
179 	ASP2_D_RX_CTRL2,
180 	ASP2_E_RX_CTRL1,
181 	ASP2_E_RX_CTRL2,
182 	ASP2_F_RX_CTRL1,
183 	ASP2_F_RX_CTRL2,
184 	ASP2_G_RX_CTRL1,
185 	ASP2_G_RX_CTRL2,
186 	ASP2_H_RX_CTRL1,
187 	ASP2_H_RX_CTRL2,
188 	CS8409_I2C_ADDR,
189 	CS8409_I2C_DATA,
190 	CS8409_I2C_CTRL,
191 	CS8409_I2C_STS,
192 	CS8409_I2C_QWRITE,
193 	CS8409_I2C_QREAD,
194 	CS8409_SPI_CTRL,
195 	CS8409_SPI_TX_DATA,
196 	CS8409_SPI_RX_DATA,
197 	CS8409_SPI_STS,
198 	CS8409_PFE_COEF_W1, /* Parametric filter engine coefficient write 1*/
199 	CS8409_PFE_COEF_W2,
200 	CS8409_PFE_CTRL1,
201 	CS8409_PFE_CTRL2,
202 	CS8409_PRE_SCALE_ATTN1,
203 	CS8409_PRE_SCALE_ATTN2,
204 	CS8409_PFE_COEF_MON1, /* Parametric filter engine coefficient monitor 1*/
205 	CS8409_PFE_COEF_MON2,
206 	CS8409_ASP1_INTRN_STS,
207 	CS8409_ASP2_INTRN_STS,
208 	CS8409_ASP1_RX_SCLK_COUNT,
209 	CS8409_ASP1_TX_SCLK_COUNT,
210 	CS8409_ASP2_RX_SCLK_COUNT,
211 	CS8409_ASP2_TX_SCLK_COUNT,
212 	CS8409_ASP_UNS_RESP_MASK,
213 	CS8409_LOOPBACK_CTRL = 0x80,
214 	CS8409_PAD_CFG_SLW_RATE_CTRL = 0x82, /* Pad Config and Slew Rate Control (CIR = 0x0082) */
215 };
216 
217 /* CS42L42 Specific Definitions */
218 
219 #define CS8409_MAX_CODECS			8
220 #define CS42L42_VOLUMES				(4U)
221 #define CS42L42_HP_VOL_REAL_MIN			(-63)
222 #define CS42L42_HP_VOL_REAL_MAX			(0)
223 #define CS42L42_AMIC_VOL_REAL_MIN		(-97)
224 #define CS42L42_AMIC_VOL_REAL_MAX		(12)
225 #define CS42L42_REG_HS_VOL_CHA			(0x2301)
226 #define CS42L42_REG_HS_VOL_CHB			(0x2303)
227 #define CS42L42_REG_HS_VOL_MASK			(0x003F)
228 #define CS42L42_REG_AMIC_VOL			(0x1D03)
229 #define CS42L42_REG_AMIC_VOL_MASK		(0x00FF)
230 #define CS42L42_HSDET_AUTO_DONE			(0x02)
231 #define CS42L42_HSTYPE_MASK			(0x03)
232 #define CS42L42_JACK_INSERTED			(0x0C)
233 #define CS42L42_JACK_REMOVED			(0x00)
234 #define CS42L42_I2C_TIMEOUT_US			(20000)
235 #define CS42L42_I2C_SLEEP_US			(2000)
236 #define CS42L42_PDN_TIMEOUT_US			(250000)
237 #define CS42L42_PDN_SLEEP_US			(2000)
238 
239 /* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */
240 
241 #define CS42L42_I2C_ADDR			(0x48 << 1)
242 #define CS8409_CS42L42_RESET			GENMASK(5, 5) /* CS8409_GPIO5 */
243 #define CS8409_CS42L42_INT			GENMASK(4, 4) /* CS8409_GPIO4 */
244 #define CS8409_CS42L42_HP_PIN_NID		CS8409_PIN_ASP1_TRANSMITTER_A
245 #define CS8409_CS42L42_SPK_PIN_NID		CS8409_PIN_ASP2_TRANSMITTER_A
246 #define CS8409_CS42L42_AMIC_PIN_NID		CS8409_PIN_ASP1_RECEIVER_A
247 #define CS8409_CS42L42_DMIC_PIN_NID		CS8409_PIN_DMIC1_IN
248 #define CS8409_CS42L42_DMIC_ADC_PIN_NID		CS8409_PIN_DMIC1
249 
250 /* Dolphin */
251 
252 #define DOLPHIN_C0_I2C_ADDR			(0x48 << 1)
253 #define DOLPHIN_C1_I2C_ADDR			(0x49 << 1)
254 #define DOLPHIN_HP_PIN_NID			CS8409_PIN_ASP1_TRANSMITTER_A
255 #define DOLPHIN_LO_PIN_NID			CS8409_PIN_ASP1_TRANSMITTER_B
256 #define DOLPHIN_AMIC_PIN_NID			CS8409_PIN_ASP1_RECEIVER_A
257 
258 #define DOLPHIN_C0_INT				GENMASK(4, 4)
259 #define DOLPHIN_C1_INT				GENMASK(0, 0)
260 #define DOLPHIN_C0_RESET			GENMASK(5, 5)
261 #define DOLPHIN_C1_RESET			GENMASK(1, 1)
262 #define DOLPHIN_WAKE				(DOLPHIN_C0_INT | DOLPHIN_C1_INT)
263 
264 enum {
265 	CS8409_BULLSEYE,
266 	CS8409_WARLOCK,
267 	CS8409_CYBORG,
268 	CS8409_FIXUPS,
269 	CS8409_DOLPHIN,
270 	CS8409_DOLPHIN_FIXUPS,
271 };
272 
273 enum {
274 	CS8409_CODEC0,
275 	CS8409_CODEC1
276 };
277 
278 enum {
279 	CS42L42_VOL_ADC,
280 	CS42L42_VOL_DAC,
281 };
282 
283 #define CS42L42_ADC_VOL_OFFSET			(CS42L42_VOL_ADC)
284 #define CS42L42_DAC_CH0_VOL_OFFSET		(CS42L42_VOL_DAC)
285 #define CS42L42_DAC_CH1_VOL_OFFSET		(CS42L42_VOL_DAC + 1)
286 
287 struct cs8409_i2c_param {
288 	unsigned int addr;
289 	unsigned int value;
290 };
291 
292 struct cs8409_cir_param {
293 	unsigned int nid;
294 	unsigned int cir;
295 	unsigned int coeff;
296 };
297 
298 struct sub_codec {
299 	struct hda_codec *codec;
300 	unsigned int addr;
301 	unsigned int reset_gpio;
302 	unsigned int irq_mask;
303 	const struct cs8409_i2c_param *init_seq;
304 	unsigned int init_seq_num;
305 
306 	unsigned int hp_jack_in:1;
307 	unsigned int mic_jack_in:1;
308 	unsigned int suspended:1;
309 	unsigned int paged:1;
310 	unsigned int last_page;
311 	unsigned int hsbias_hiz;
312 	unsigned int full_scale_vol:1;
313 	unsigned int no_type_dect:1;
314 
315 	s8 vol[CS42L42_VOLUMES];
316 };
317 
318 struct cs8409_spec {
319 	struct hda_gen_spec gen;
320 	struct hda_codec *codec;
321 
322 	struct sub_codec *scodecs[CS8409_MAX_CODECS];
323 	unsigned int num_scodecs;
324 
325 	unsigned int gpio_mask;
326 	unsigned int gpio_dir;
327 	unsigned int gpio_data;
328 
329 	struct mutex i2c_mux;
330 	unsigned int i2c_clck_enabled;
331 	unsigned int dev_addr;
332 	struct delayed_work i2c_clk_work;
333 
334 	unsigned int playback_started:1;
335 	unsigned int capture_started:1;
336 	unsigned int init_done:1;
337 	unsigned int build_ctrl_done:1;
338 
339 	/* verb exec op override */
340 	int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
341 			 unsigned int *res);
342 };
343 
344 extern const struct snd_kcontrol_new cs42l42_dac_volume_mixer;
345 extern const struct snd_kcontrol_new cs42l42_adc_volume_mixer;
346 
347 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo);
348 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
349 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
350 
351 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback;
352 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture;
353 extern const struct snd_pci_quirk cs8409_fixup_tbl[];
354 extern const struct hda_model_fixup cs8409_models[];
355 extern const struct hda_fixup cs8409_fixups[];
356 extern const struct hda_verb cs8409_cs42l42_init_verbs[];
357 extern const struct hda_pintbl cs8409_cs42l42_pincfgs[];
358 extern const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[];
359 extern const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[];
360 extern struct sub_codec cs8409_cs42l42_codec;
361 
362 extern const struct hda_verb dolphin_init_verbs[];
363 extern const struct hda_pintbl dolphin_pincfgs[];
364 extern const struct cs8409_cir_param dolphin_hw_cfg[];
365 extern struct sub_codec dolphin_cs42l42_0;
366 extern struct sub_codec dolphin_cs42l42_1;
367 
368 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);
369 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);
370 
371 #endif
372