1 /* SPDX-License-Identifier: GPL-2.0 */
2 #define CS4245_CHIP_ID		0x01
3 #define CS4245_POWER_CTRL	0x02
4 #define CS4245_DAC_CTRL_1	0x03
5 #define CS4245_ADC_CTRL		0x04
6 #define CS4245_MCLK_FREQ	0x05
7 #define CS4245_SIGNAL_SEL	0x06
8 #define CS4245_PGA_B_CTRL	0x07
9 #define CS4245_PGA_A_CTRL	0x08
10 #define CS4245_ANALOG_IN	0x09
11 #define CS4245_DAC_A_CTRL	0x0a
12 #define CS4245_DAC_B_CTRL	0x0b
13 #define CS4245_DAC_CTRL_2	0x0c
14 #define CS4245_INT_STATUS	0x0d
15 #define CS4245_INT_MASK		0x0e
16 #define CS4245_INT_MODE_MSB	0x0f
17 #define CS4245_INT_MODE_LSB	0x10
18 
19 /* Chip ID */
20 #define CS4245_CHIP_PART_MASK	0xf0
21 #define CS4245_CHIP_REV_MASK	0x0f
22 
23 /* Power Control */
24 #define CS4245_FREEZE		0x80
25 #define CS4245_PDN_MIC		0x08
26 #define CS4245_PDN_ADC		0x04
27 #define CS4245_PDN_DAC		0x02
28 #define CS4245_PDN		0x01
29 
30 /* DAC Control */
31 #define CS4245_DAC_FM_MASK	0xc0
32 #define CS4245_DAC_FM_SINGLE	0x00
33 #define CS4245_DAC_FM_DOUBLE	0x40
34 #define CS4245_DAC_FM_QUAD	0x80
35 #define CS4245_DAC_DIF_MASK	0x30
36 #define CS4245_DAC_DIF_LJUST	0x00
37 #define CS4245_DAC_DIF_I2S	0x10
38 #define CS4245_DAC_DIF_RJUST_16	0x20
39 #define CS4245_DAC_DIF_RJUST_24	0x30
40 #define CS4245_RESERVED_1	0x08
41 #define CS4245_MUTE_DAC		0x04
42 #define CS4245_DEEMPH		0x02
43 #define CS4245_DAC_MASTER	0x01
44 
45 /* ADC Control */
46 #define CS4245_ADC_FM_MASK	0xc0
47 #define CS4245_ADC_FM_SINGLE	0x00
48 #define CS4245_ADC_FM_DOUBLE	0x40
49 #define CS4245_ADC_FM_QUAD	0x80
50 #define CS4245_ADC_DIF_MASK	0x10
51 #define CS4245_ADC_DIF_LJUST	0x00
52 #define CS4245_ADC_DIF_I2S	0x10
53 #define CS4245_MUTE_ADC		0x04
54 #define CS4245_HPF_FREEZE	0x02
55 #define CS4245_ADC_MASTER	0x01
56 
57 /* MCLK Frequency */
58 #define CS4245_MCLK1_MASK	0x70
59 #define CS4245_MCLK1_SHIFT	4
60 #define CS4245_MCLK2_MASK	0x07
61 #define CS4245_MCLK2_SHIFT	0
62 #define CS4245_MCLK_1		0
63 #define CS4245_MCLK_1_5		1
64 #define CS4245_MCLK_2		2
65 #define CS4245_MCLK_3		3
66 #define CS4245_MCLK_4		4
67 
68 /* Signal Selection */
69 #define CS4245_A_OUT_SEL_MASK	0x60
70 #define CS4245_A_OUT_SEL_HIZ	0x00
71 #define CS4245_A_OUT_SEL_DAC	0x20
72 #define CS4245_A_OUT_SEL_PGA	0x40
73 #define CS4245_LOOP		0x02
74 #define CS4245_ASYNCH		0x01
75 
76 /* Channel B/A PGA Control */
77 #define CS4245_PGA_GAIN_MASK	0x3f
78 
79 /* ADC Input Control */
80 #define CS4245_PGA_SOFT		0x10
81 #define CS4245_PGA_ZERO		0x08
82 #define CS4245_SEL_MASK		0x07
83 #define CS4245_SEL_MIC		0x00
84 #define CS4245_SEL_INPUT_1	0x01
85 #define CS4245_SEL_INPUT_2	0x02
86 #define CS4245_SEL_INPUT_3	0x03
87 #define CS4245_SEL_INPUT_4	0x04
88 #define CS4245_SEL_INPUT_5	0x05
89 #define CS4245_SEL_INPUT_6	0x06
90 
91 /* DAC Channel A/B Volume Control */
92 #define CS4245_VOL_MASK		0xff
93 
94 /* DAC Control 2 */
95 #define CS4245_DAC_SOFT		0x80
96 #define CS4245_DAC_ZERO		0x40
97 #define CS4245_INVERT_DAC	0x20
98 #define CS4245_INT_ACTIVE_HIGH	0x01
99 
100 /* Interrupt Status/Mask/Mode */
101 #define CS4245_ADC_CLK_ERR	0x08
102 #define CS4245_DAC_CLK_ERR	0x04
103 #define CS4245_ADC_OVFL		0x02
104 #define CS4245_ADC_UNDRFL	0x01
105 
106 #define CS4245_SPI_ADDRESS_S	(0x9e << 16)
107 #define CS4245_SPI_WRITE_S	(0 << 16)
108 
109 #define CS4245_SPI_ADDRESS	0x9e
110 #define CS4245_SPI_WRITE	0
111 #define CS4245_SPI_READ		1
112