1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * Copyright(c) 2017 Intel Corporation. All rights reserved.
7  *
8  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9  */
10 
11 #ifndef __SOF_INTEL_SHIM_H
12 #define __SOF_INTEL_SHIM_H
13 
14 /*
15  * SHIM registers for BYT, BSW, CHT, BDW
16  */
17 
18 #define SHIM_CSR		(SHIM_OFFSET + 0x00)
19 #define SHIM_PISR		(SHIM_OFFSET + 0x08)
20 #define SHIM_PIMR		(SHIM_OFFSET + 0x10)
21 #define SHIM_ISRX		(SHIM_OFFSET + 0x18)
22 #define SHIM_ISRD		(SHIM_OFFSET + 0x20)
23 #define SHIM_IMRX		(SHIM_OFFSET + 0x28)
24 #define SHIM_IMRD		(SHIM_OFFSET + 0x30)
25 #define SHIM_IPCX		(SHIM_OFFSET + 0x38)
26 #define SHIM_IPCD		(SHIM_OFFSET + 0x40)
27 #define SHIM_ISRSC		(SHIM_OFFSET + 0x48)
28 #define SHIM_ISRLPESC		(SHIM_OFFSET + 0x50)
29 #define SHIM_IMRSC		(SHIM_OFFSET + 0x58)
30 #define SHIM_IMRLPESC		(SHIM_OFFSET + 0x60)
31 #define SHIM_IPCSC		(SHIM_OFFSET + 0x68)
32 #define SHIM_IPCLPESC		(SHIM_OFFSET + 0x70)
33 #define SHIM_CLKCTL		(SHIM_OFFSET + 0x78)
34 #define SHIM_CSR2		(SHIM_OFFSET + 0x80)
35 #define SHIM_LTRC		(SHIM_OFFSET + 0xE0)
36 #define SHIM_HMDC		(SHIM_OFFSET + 0xE8)
37 
38 #define SHIM_PWMCTRL		0x1000
39 
40 /*
41  * SST SHIM register bits for BYT, BSW, CHT, BDW
42  * Register bit naming and functionaility can differ between devices.
43  */
44 
45 /* CSR / CS */
46 #define SHIM_CSR_RST		BIT(1)
47 #define SHIM_CSR_SBCS0		BIT(2)
48 #define SHIM_CSR_SBCS1		BIT(3)
49 #define SHIM_CSR_DCS(x)		((x) << 4)
50 #define SHIM_CSR_DCS_MASK	(0x7 << 4)
51 #define SHIM_CSR_STALL		BIT(10)
52 #define SHIM_CSR_S0IOCS		BIT(21)
53 #define SHIM_CSR_S1IOCS		BIT(23)
54 #define SHIM_CSR_LPCS		BIT(31)
55 #define SHIM_CSR_24MHZ_LPCS \
56 	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
57 #define SHIM_CSR_24MHZ_NO_LPCS	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
58 #define SHIM_BYT_CSR_RST	BIT(0)
59 #define SHIM_BYT_CSR_VECTOR_SEL	BIT(1)
60 #define SHIM_BYT_CSR_STALL	BIT(2)
61 #define SHIM_BYT_CSR_PWAITMODE	BIT(3)
62 
63 /*  ISRX / ISC */
64 #define SHIM_ISRX_BUSY		BIT(1)
65 #define SHIM_ISRX_DONE		BIT(0)
66 #define SHIM_BYT_ISRX_REQUEST	BIT(1)
67 
68 /*  ISRD / ISD */
69 #define SHIM_ISRD_BUSY		BIT(1)
70 #define SHIM_ISRD_DONE		BIT(0)
71 
72 /* IMRX / IMC */
73 #define SHIM_IMRX_BUSY		BIT(1)
74 #define SHIM_IMRX_DONE		BIT(0)
75 #define SHIM_BYT_IMRX_REQUEST	BIT(1)
76 
77 /* IMRD / IMD */
78 #define SHIM_IMRD_DONE		BIT(0)
79 #define SHIM_IMRD_BUSY		BIT(1)
80 #define SHIM_IMRD_SSP0		BIT(16)
81 #define SHIM_IMRD_DMAC0		BIT(21)
82 #define SHIM_IMRD_DMAC1		BIT(22)
83 #define SHIM_IMRD_DMAC		(SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
84 
85 /*  IPCX / IPCC */
86 #define	SHIM_IPCX_DONE		BIT(30)
87 #define	SHIM_IPCX_BUSY		BIT(31)
88 #define SHIM_BYT_IPCX_DONE	BIT_ULL(62)
89 #define SHIM_BYT_IPCX_BUSY	BIT_ULL(63)
90 
91 /*  IPCD */
92 #define	SHIM_IPCD_DONE		BIT(30)
93 #define	SHIM_IPCD_BUSY		BIT(31)
94 #define SHIM_BYT_IPCD_DONE	BIT_ULL(62)
95 #define SHIM_BYT_IPCD_BUSY	BIT_ULL(63)
96 
97 /* CLKCTL */
98 #define SHIM_CLKCTL_SMOS(x)	((x) << 24)
99 #define SHIM_CLKCTL_MASK	(3 << 24)
100 #define SHIM_CLKCTL_DCPLCG	BIT(18)
101 #define SHIM_CLKCTL_SCOE1	BIT(17)
102 #define SHIM_CLKCTL_SCOE0	BIT(16)
103 
104 /* CSR2 / CS2 */
105 #define SHIM_CSR2_SDFD_SSP0	BIT(1)
106 #define SHIM_CSR2_SDFD_SSP1	BIT(2)
107 
108 /* LTRC */
109 #define SHIM_LTRC_VAL(x)	((x) << 0)
110 
111 /* HMDC */
112 #define SHIM_HMDC_HDDA0(x)	((x) << 0)
113 #define SHIM_HMDC_HDDA1(x)	((x) << 7)
114 #define SHIM_HMDC_HDDA_E0_CH0	1
115 #define SHIM_HMDC_HDDA_E0_CH1	2
116 #define SHIM_HMDC_HDDA_E0_CH2	4
117 #define SHIM_HMDC_HDDA_E0_CH3	8
118 #define SHIM_HMDC_HDDA_E1_CH0	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0)
119 #define SHIM_HMDC_HDDA_E1_CH1	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1)
120 #define SHIM_HMDC_HDDA_E1_CH2	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2)
121 #define SHIM_HMDC_HDDA_E1_CH3	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3)
122 #define SHIM_HMDC_HDDA_E0_ALLCH	\
123 	(SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \
124 	 SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3)
125 #define SHIM_HMDC_HDDA_E1_ALLCH	\
126 	(SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \
127 	 SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3)
128 
129 /* Audio DSP PCI registers */
130 #define PCI_VDRTCTL0		0xa0
131 #define PCI_VDRTCTL1		0xa4
132 #define PCI_VDRTCTL2		0xa8
133 #define PCI_VDRTCTL3		0xaC
134 
135 /* VDRTCTL0 */
136 #define PCI_VDRTCL0_D3PGD		BIT(0)
137 #define PCI_VDRTCL0_D3SRAMPGD		BIT(1)
138 #define PCI_VDRTCL0_DSRAMPGE_SHIFT	12
139 #define PCI_VDRTCL0_DSRAMPGE_MASK	GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
140 						PCI_VDRTCL0_DSRAMPGE_SHIFT)
141 #define PCI_VDRTCL0_ISRAMPGE_SHIFT	2
142 #define PCI_VDRTCL0_ISRAMPGE_MASK	GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
143 						PCI_VDRTCL0_ISRAMPGE_SHIFT)
144 
145 /* VDRTCTL2 */
146 #define PCI_VDRTCL2_DCLCGE		BIT(1)
147 #define PCI_VDRTCL2_DTCGE		BIT(10)
148 #define PCI_VDRTCL2_APLLSE_MASK		BIT(31)
149 
150 /* PMCS */
151 #define PCI_PMCS		0x84
152 #define PCI_PMCS_PS_MASK	0x3
153 
154 /* DSP hardware descriptor */
155 struct sof_intel_dsp_desc {
156 	int cores_num;
157 	int host_managed_cores_mask;
158 	int init_core_mask; /* cores available after fw boot */
159 	int ipc_req;
160 	int ipc_req_mask;
161 	int ipc_ack;
162 	int ipc_ack_mask;
163 	int ipc_ctl;
164 	int rom_init_timeout;
165 	int ssp_count;			/* ssp count of the platform */
166 	int ssp_base_offset;		/* base address of the SSPs */
167 	u32 sdw_shim_base;
168 	u32 sdw_alh_base;
169 	bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
170 };
171 
172 extern const struct snd_sof_dsp_ops sof_tng_ops;
173 
174 extern const struct sof_intel_dsp_desc tng_chip_info;
175 
176 struct sof_intel_stream {
177 	size_t posn_offset;
178 };
179 
180 #endif
181