1[ 2 { 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", 4 "Counter": "0,1,2,3", 5 "CounterType": "PGMABLE", 6 "EventCode": "0x04", 7 "EventName": "LLC_MISSES.MEM_READ", 8 "PerPkg": "1", 9 "ScaleUnit": "64Bytes", 10 "UMask": "0x0f", 11 "Unit": "iMC" 12 }, 13 { 14 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 15 "Counter": "0,1,2,3", 16 "CounterType": "PGMABLE", 17 "EventCode": "0x04", 18 "EventName": "LLC_MISSES.MEM_WRITE", 19 "PerPkg": "1", 20 "ScaleUnit": "64Bytes", 21 "UMask": "0x30", 22 "Unit": "iMC" 23 }, 24 { 25 "BriefDescription": "Memory controller clock ticks", 26 "Counter": "0,1,2,3", 27 "CounterType": "PGMABLE", 28 "EventName": "UNC_M_CLOCKTICKS", 29 "PerPkg": "1", 30 "Unit": "iMC" 31 }, 32 { 33 "BriefDescription": "Pre-charge for reads", 34 "Counter": "0,1,2,3", 35 "CounterType": "PGMABLE", 36 "EventCode": "0x02", 37 "EventName": "UNC_M_PRE_COUNT.RD", 38 "PerPkg": "1", 39 "UMask": "0x04", 40 "Unit": "iMC" 41 }, 42 { 43 "BriefDescription": "Pre-charge for writes", 44 "Counter": "0,1,2,3", 45 "CounterType": "PGMABLE", 46 "EventCode": "0x02", 47 "EventName": "UNC_M_PRE_COUNT.WR", 48 "PerPkg": "1", 49 "UMask": "0x08", 50 "Unit": "iMC" 51 }, 52 { 53 "BriefDescription": "Precharge due to read on page miss, write on page miss or PGT", 54 "Counter": "0,1,2,3", 55 "CounterType": "PGMABLE", 56 "EventCode": "0x02", 57 "EventName": "UNC_M_PRE_COUNT.ALL", 58 "PerPkg": "1", 59 "UMask": "0x1c", 60 "Unit": "iMC" 61 }, 62 { 63 "BriefDescription": "DRAM Precharge commands. : Precharge due to page table", 64 "Counter": "0,1,2,3", 65 "CounterType": "PGMABLE", 66 "EventCode": "0x02", 67 "EventName": "UNC_M_PRE_COUNT.PGT", 68 "PerPkg": "1", 69 "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel.", 70 "UMask": "0x10", 71 "Unit": "iMC" 72 } 73] 74