1[ 2 { 3 "BriefDescription": "Uncore cache clock ticks", 4 "Counter": "0,1,2,3", 5 "CounterType": "PGMABLE", 6 "EventName": "UNC_CHA_CLOCKTICKS", 7 "PerPkg": "1", 8 "Unit": "CHA" 9 }, 10 { 11 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", 12 "Counter": "0,1,2,3", 13 "CounterType": "PGMABLE", 14 "EventCode": "0x35", 15 "EventName": "LLC_MISSES.UNCACHEABLE", 16 "Filter": "config1=0x40e33", 17 "PerPkg": "1", 18 "UMask": "0xC001FE01", 19 "UMaskExt": "0xC001FE", 20 "Unit": "CHA" 21 }, 22 { 23 "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss", 24 "Counter": "0,1,2,3", 25 "CounterType": "PGMABLE", 26 "EventCode": "0x35", 27 "EventName": "LLC_MISSES.MMIO_READ", 28 "Filter": "config1=0x40040e33", 29 "PerPkg": "1", 30 "UMask": "0xC001FE01", 31 "UMaskExt": "0xC001FE", 32 "Unit": "CHA" 33 }, 34 { 35 "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss", 36 "Counter": "0,1,2,3", 37 "CounterType": "PGMABLE", 38 "EventCode": "0x35", 39 "EventName": "LLC_MISSES.MMIO_WRITE", 40 "Filter": "config1=0x40041e33", 41 "PerPkg": "1", 42 "UMask": "0xC001FE01", 43 "UMaskExt": "0xC001FE", 44 "Unit": "CHA" 45 }, 46 { 47 "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss", 48 "Counter": "0,1,2,3", 49 "CounterType": "PGMABLE", 50 "EventCode": "0x35", 51 "EventName": "LLC_REFERENCES.STREAMING_FULL", 52 "Filter": "config1=0x41833", 53 "PerPkg": "1", 54 "ScaleUnit": "64Bytes", 55 "UMask": "0xC001FE01", 56 "UMaskExt": "0xC001FE", 57 "Unit": "CHA" 58 }, 59 { 60 "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss", 61 "Counter": "0,1,2,3", 62 "CounterType": "PGMABLE", 63 "EventCode": "0x35", 64 "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", 65 "Filter": "config1=0x41a33", 66 "PerPkg": "1", 67 "ScaleUnit": "64Bytes", 68 "UMask": "0xC001FE01", 69 "UMaskExt": "0xC001FE", 70 "Unit": "CHA" 71 }, 72 { 73 "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", 74 "Counter": "0,1", 75 "CounterType": "PGMABLE", 76 "EventCode": "0x83", 77 "EventName": "LLC_MISSES.PCIE_READ", 78 "FCMask": "0x07", 79 "Filter": "ch_mask=0x1f", 80 "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", 81 "MetricName": "LLC_MISSES.PCIE_READ", 82 "PerPkg": "1", 83 "PortMask": "0x01", 84 "ScaleUnit": "4Bytes", 85 "UMask": "0x04", 86 "Unit": "IIO" 87 }, 88 { 89 "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", 90 "Counter": "0,1", 91 "CounterType": "PGMABLE", 92 "EventCode": "0x83", 93 "EventName": "LLC_MISSES.PCIE_WRITE", 94 "FCMask": "0x07", 95 "Filter": "ch_mask=0x1f", 96 "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", 97 "MetricName": "LLC_MISSES.PCIE_WRITE", 98 "PerPkg": "1", 99 "PortMask": "0x01", 100 "ScaleUnit": "4Bytes", 101 "UMask": "0x01", 102 "Unit": "IIO" 103 }, 104 { 105 "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", 106 "Counter": "0,1", 107 "CounterType": "PGMABLE", 108 "EventCode": "0x83", 109 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", 110 "FCMask": "0x07", 111 "PerPkg": "1", 112 "PortMask": "0x02", 113 "ScaleUnit": "4Bytes", 114 "UMask": "0x01", 115 "Unit": "IIO" 116 }, 117 { 118 "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", 119 "Counter": "0,1", 120 "CounterType": "PGMABLE", 121 "EventCode": "0x83", 122 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", 123 "FCMask": "0x07", 124 "PerPkg": "1", 125 "PortMask": "0x04", 126 "ScaleUnit": "4Bytes", 127 "UMask": "0x01", 128 "Unit": "IIO" 129 }, 130 { 131 "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", 132 "Counter": "0,1", 133 "CounterType": "PGMABLE", 134 "EventCode": "0x83", 135 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", 136 "FCMask": "0x07", 137 "PerPkg": "1", 138 "PortMask": "0x08", 139 "ScaleUnit": "4Bytes", 140 "UMask": "0x01", 141 "Unit": "IIO" 142 }, 143 { 144 "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", 145 "Counter": "0,1", 146 "CounterType": "PGMABLE", 147 "EventCode": "0x83", 148 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", 149 "FCMask": "0x07", 150 "PerPkg": "1", 151 "PortMask": "0x02", 152 "ScaleUnit": "4Bytes", 153 "UMask": "0x04", 154 "Unit": "IIO" 155 }, 156 { 157 "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", 158 "Counter": "0,1", 159 "CounterType": "PGMABLE", 160 "EventCode": "0x83", 161 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", 162 "FCMask": "0x07", 163 "PerPkg": "1", 164 "PortMask": "0x04", 165 "ScaleUnit": "4Bytes", 166 "UMask": "0x04", 167 "Unit": "IIO" 168 }, 169 { 170 "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", 171 "Counter": "0,1", 172 "CounterType": "PGMABLE", 173 "EventCode": "0x83", 174 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", 175 "FCMask": "0x07", 176 "PerPkg": "1", 177 "PortMask": "0x08", 178 "ScaleUnit": "4Bytes", 179 "UMask": "0x04", 180 "Unit": "IIO" 181 }, 182 { 183 "BriefDescription": "TOR Inserts; CRd misses from local IA", 184 "Counter": "0,1,2,3", 185 "CounterType": "PGMABLE", 186 "EventCode": "0x35", 187 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", 188 "PerPkg": "1", 189 "PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter", 190 "UMask": "0xC80FFE01", 191 "UMaskExt": "0xC80FFE", 192 "Unit": "CHA" 193 }, 194 { 195 "BriefDescription": "TOR Inserts; CRd Pref misses from local IA", 196 "Counter": "0,1,2,3", 197 "CounterType": "PGMABLE", 198 "EventCode": "0x35", 199 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", 200 "PerPkg": "1", 201 "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", 202 "UMask": "0xC88FFE01", 203 "UMaskExt": "0xC88FFE", 204 "Unit": "CHA" 205 }, 206 { 207 "BriefDescription": "TOR Inserts; DRd Opt misses from local IA", 208 "Counter": "0,1,2,3", 209 "CounterType": "PGMABLE", 210 "EventCode": "0x35", 211 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", 212 "PerPkg": "1", 213 "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter", 214 "UMask": "0xC827FE01", 215 "UMaskExt": "0xC827FE", 216 "Unit": "CHA" 217 }, 218 { 219 "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA", 220 "Counter": "0,1,2,3", 221 "CounterType": "PGMABLE", 222 "EventCode": "0x35", 223 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", 224 "PerPkg": "1", 225 "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter", 226 "UMask": "0xC8A7FE01", 227 "UMaskExt": "0xC8A7FE", 228 "Unit": "CHA" 229 }, 230 { 231 "BriefDescription": "TOR Inserts; RFO misses from local IA", 232 "Counter": "0,1,2,3", 233 "CounterType": "PGMABLE", 234 "EventCode": "0x35", 235 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", 236 "PerPkg": "1", 237 "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", 238 "UMask": "0xC807FE01", 239 "UMaskExt": "0xC807FE", 240 "Unit": "CHA" 241 }, 242 { 243 "BriefDescription": "TOR Inserts; RFO pref misses from local IA", 244 "Counter": "0,1,2,3", 245 "CounterType": "PGMABLE", 246 "EventCode": "0x35", 247 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", 248 "PerPkg": "1", 249 "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", 250 "UMask": "0xC887FE01", 251 "UMaskExt": "0xC887FE", 252 "Unit": "CHA" 253 }, 254 { 255 "BriefDescription": "TOR Inserts; WCiL misses from local IA", 256 "Counter": "0,1,2,3", 257 "CounterType": "PGMABLE", 258 "EventCode": "0x35", 259 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", 260 "PerPkg": "1", 261 "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", 262 "UMask": "0xC86FFE01", 263 "UMaskExt": "0xC86FFE", 264 "Unit": "CHA" 265 }, 266 { 267 "BriefDescription": "TOR Inserts; WCiLF misses from local IA", 268 "Counter": "0,1,2,3", 269 "CounterType": "PGMABLE", 270 "EventCode": "0x35", 271 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", 272 "PerPkg": "1", 273 "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", 274 "UMask": "0xC867FE01", 275 "UMaskExt": "0xC867FE", 276 "Unit": "CHA" 277 }, 278 { 279 "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", 280 "Counter": "0,1,2,3", 281 "CounterType": "PGMABLE", 282 "EventCode": "0x01", 283 "EventName": "UNC_IIO_CLOCKTICKS", 284 "PerPkg": "1", 285 "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller", 286 "Unit": "IIO" 287 }, 288 { 289 "BriefDescription": "Data requested of the CPU : Card reading from DRAM", 290 "Counter": "0,1", 291 "CounterType": "PGMABLE", 292 "EventCode": "0x83", 293 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", 294 "FCMask": "0x07", 295 "PerPkg": "1", 296 "PortMask": "0x10", 297 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", 298 "UMask": "0x04", 299 "Unit": "IIO" 300 }, 301 { 302 "BriefDescription": "Data requested of the CPU : Card reading from DRAM", 303 "Counter": "0,1", 304 "CounterType": "PGMABLE", 305 "EventCode": "0x83", 306 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", 307 "FCMask": "0x07", 308 "PerPkg": "1", 309 "PortMask": "0x20", 310 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", 311 "UMask": "0x04", 312 "Unit": "IIO" 313 }, 314 { 315 "BriefDescription": "Data requested of the CPU : Card reading from DRAM", 316 "Counter": "0,1", 317 "CounterType": "PGMABLE", 318 "EventCode": "0x83", 319 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", 320 "FCMask": "0x07", 321 "PerPkg": "1", 322 "PortMask": "0x40", 323 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", 324 "UMask": "0x04", 325 "Unit": "IIO" 326 }, 327 { 328 "BriefDescription": "Data requested of the CPU : Card reading from DRAM", 329 "Counter": "0,1", 330 "CounterType": "PGMABLE", 331 "EventCode": "0x83", 332 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", 333 "FCMask": "0x07", 334 "PerPkg": "1", 335 "PortMask": "0x80", 336 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", 337 "UMask": "0x04", 338 "Unit": "IIO" 339 }, 340 { 341 "BriefDescription": "Data requested of the CPU : Card writing to DRAM", 342 "Counter": "0,1", 343 "CounterType": "PGMABLE", 344 "EventCode": "0x83", 345 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", 346 "FCMask": "0x07", 347 "PerPkg": "1", 348 "PortMask": "0x10", 349 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", 350 "UMask": "0x01", 351 "Unit": "IIO" 352 }, 353 { 354 "BriefDescription": "Data requested of the CPU : Card writing to DRAM", 355 "Counter": "0,1", 356 "CounterType": "PGMABLE", 357 "EventCode": "0x83", 358 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", 359 "FCMask": "0x07", 360 "PerPkg": "1", 361 "PortMask": "0x20", 362 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", 363 "UMask": "0x01", 364 "Unit": "IIO" 365 }, 366 { 367 "BriefDescription": "Data requested of the CPU : Card writing to DRAM", 368 "Counter": "0,1", 369 "CounterType": "PGMABLE", 370 "EventCode": "0x83", 371 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", 372 "FCMask": "0x07", 373 "PerPkg": "1", 374 "PortMask": "0x40", 375 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", 376 "UMask": "0x01", 377 "Unit": "IIO" 378 }, 379 { 380 "BriefDescription": "Data requested of the CPU : Card writing to DRAM", 381 "Counter": "0,1", 382 "CounterType": "PGMABLE", 383 "EventCode": "0x83", 384 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", 385 "FCMask": "0x07", 386 "PerPkg": "1", 387 "PortMask": "0x80", 388 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", 389 "UMask": "0x01", 390 "Unit": "IIO" 391 }, 392 { 393 "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", 394 "Counter": "0,1", 395 "CounterType": "PGMABLE", 396 "EventCode": "0x01", 397 "EventName": "UNC_I_CLOCKTICKS", 398 "PerPkg": "1", 399 "PublicDescription": "Clockticks of the IO coherency tracker (IRP)", 400 "Unit": "IRP" 401 }, 402 { 403 "BriefDescription": "Clockticks of the mesh to memory (M2M)", 404 "Counter": "0,1,2,3", 405 "CounterType": "PGMABLE", 406 "EventName": "UNC_M2M_CLOCKTICKS", 407 "PerPkg": "1", 408 "PublicDescription": "Clockticks of the mesh to memory (M2M)", 409 "Unit": "M2M" 410 }, 411 { 412 "BriefDescription": "Clockticks of the mesh to PCI (M2P)", 413 "Counter": "0,1,2,3", 414 "CounterType": "PGMABLE", 415 "EventCode": "0x01", 416 "EventName": "UNC_M2P_CLOCKTICKS", 417 "PerPkg": "1", 418 "PublicDescription": "Clockticks of the mesh to PCI (M2P)", 419 "Unit": "M2PCIe" 420 }, 421 { 422 "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", 423 "Counter": "FIXED", 424 "CounterType": "PGMABLE", 425 "EventCode": "0xff", 426 "EventName": "UNC_U_CLOCKTICKS", 427 "PerPkg": "1", 428 "PublicDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", 429 "Unit": "UBOX" 430 } 431] 432