1[ 2 { 3 "EventCode": "0x63", 4 "Counter": "0,1", 5 "UMask": "0x2", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "BriefDescription": "Cycles L1D locked" 9 }, 10 { 11 "EventCode": "0x63", 12 "Counter": "0,1", 13 "UMask": "0x1", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "BriefDescription": "Cycles L1D and L2 locked" 17 }, 18 { 19 "EventCode": "0x51", 20 "Counter": "0,1", 21 "UMask": "0x4", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "BriefDescription": "L1D cache lines replaced in M state" 25 }, 26 { 27 "EventCode": "0x51", 28 "Counter": "0,1", 29 "UMask": "0x2", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "BriefDescription": "L1D cache lines allocated in the M state" 33 }, 34 { 35 "EventCode": "0x51", 36 "Counter": "0,1", 37 "UMask": "0x8", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "BriefDescription": "L1D snoop eviction of cache lines in M state" 41 }, 42 { 43 "EventCode": "0x51", 44 "Counter": "0,1", 45 "UMask": "0x1", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "BriefDescription": "L1 data cache lines allocated" 49 }, 50 { 51 "EventCode": "0x52", 52 "Counter": "0,1", 53 "UMask": "0x1", 54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 55 "SampleAfterValue": "2000000", 56 "BriefDescription": "L1D prefetch load lock accepted in fill buffer" 57 }, 58 { 59 "EventCode": "0x4E", 60 "Counter": "0,1", 61 "UMask": "0x2", 62 "EventName": "L1D_PREFETCH.MISS", 63 "SampleAfterValue": "200000", 64 "BriefDescription": "L1D hardware prefetch misses" 65 }, 66 { 67 "EventCode": "0x4E", 68 "Counter": "0,1", 69 "UMask": "0x1", 70 "EventName": "L1D_PREFETCH.REQUESTS", 71 "SampleAfterValue": "200000", 72 "BriefDescription": "L1D hardware prefetch requests" 73 }, 74 { 75 "EventCode": "0x4E", 76 "Counter": "0,1", 77 "UMask": "0x4", 78 "EventName": "L1D_PREFETCH.TRIGGERS", 79 "SampleAfterValue": "200000", 80 "BriefDescription": "L1D hardware prefetch requests triggered" 81 }, 82 { 83 "EventCode": "0x28", 84 "Counter": "0,1,2,3", 85 "UMask": "0x4", 86 "EventName": "L1D_WB_L2.E_STATE", 87 "SampleAfterValue": "100000", 88 "BriefDescription": "L1 writebacks to L2 in E state" 89 }, 90 { 91 "EventCode": "0x28", 92 "Counter": "0,1,2,3", 93 "UMask": "0x1", 94 "EventName": "L1D_WB_L2.I_STATE", 95 "SampleAfterValue": "100000", 96 "BriefDescription": "L1 writebacks to L2 in I state (misses)" 97 }, 98 { 99 "EventCode": "0x28", 100 "Counter": "0,1,2,3", 101 "UMask": "0x8", 102 "EventName": "L1D_WB_L2.M_STATE", 103 "SampleAfterValue": "100000", 104 "BriefDescription": "L1 writebacks to L2 in M state" 105 }, 106 { 107 "EventCode": "0x28", 108 "Counter": "0,1,2,3", 109 "UMask": "0xf", 110 "EventName": "L1D_WB_L2.MESI", 111 "SampleAfterValue": "100000", 112 "BriefDescription": "All L1 writebacks to L2" 113 }, 114 { 115 "EventCode": "0x28", 116 "Counter": "0,1,2,3", 117 "UMask": "0x2", 118 "EventName": "L1D_WB_L2.S_STATE", 119 "SampleAfterValue": "100000", 120 "BriefDescription": "L1 writebacks to L2 in S state" 121 }, 122 { 123 "EventCode": "0x26", 124 "Counter": "0,1,2,3", 125 "UMask": "0xff", 126 "EventName": "L2_DATA_RQSTS.ANY", 127 "SampleAfterValue": "200000", 128 "BriefDescription": "All L2 data requests" 129 }, 130 { 131 "EventCode": "0x26", 132 "Counter": "0,1,2,3", 133 "UMask": "0x4", 134 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 135 "SampleAfterValue": "200000", 136 "BriefDescription": "L2 data demand loads in E state" 137 }, 138 { 139 "EventCode": "0x26", 140 "Counter": "0,1,2,3", 141 "UMask": "0x1", 142 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 143 "SampleAfterValue": "200000", 144 "BriefDescription": "L2 data demand loads in I state (misses)" 145 }, 146 { 147 "EventCode": "0x26", 148 "Counter": "0,1,2,3", 149 "UMask": "0x8", 150 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 151 "SampleAfterValue": "200000", 152 "BriefDescription": "L2 data demand loads in M state" 153 }, 154 { 155 "EventCode": "0x26", 156 "Counter": "0,1,2,3", 157 "UMask": "0xf", 158 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 159 "SampleAfterValue": "200000", 160 "BriefDescription": "L2 data demand requests" 161 }, 162 { 163 "EventCode": "0x26", 164 "Counter": "0,1,2,3", 165 "UMask": "0x2", 166 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 167 "SampleAfterValue": "200000", 168 "BriefDescription": "L2 data demand loads in S state" 169 }, 170 { 171 "EventCode": "0x26", 172 "Counter": "0,1,2,3", 173 "UMask": "0x40", 174 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 175 "SampleAfterValue": "200000", 176 "BriefDescription": "L2 data prefetches in E state" 177 }, 178 { 179 "EventCode": "0x26", 180 "Counter": "0,1,2,3", 181 "UMask": "0x10", 182 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 183 "SampleAfterValue": "200000", 184 "BriefDescription": "L2 data prefetches in the I state (misses)" 185 }, 186 { 187 "EventCode": "0x26", 188 "Counter": "0,1,2,3", 189 "UMask": "0x80", 190 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 191 "SampleAfterValue": "200000", 192 "BriefDescription": "L2 data prefetches in M state" 193 }, 194 { 195 "EventCode": "0x26", 196 "Counter": "0,1,2,3", 197 "UMask": "0xf0", 198 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 199 "SampleAfterValue": "200000", 200 "BriefDescription": "All L2 data prefetches" 201 }, 202 { 203 "EventCode": "0x26", 204 "Counter": "0,1,2,3", 205 "UMask": "0x20", 206 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 207 "SampleAfterValue": "200000", 208 "BriefDescription": "L2 data prefetches in the S state" 209 }, 210 { 211 "EventCode": "0xF1", 212 "Counter": "0,1,2,3", 213 "UMask": "0x7", 214 "EventName": "L2_LINES_IN.ANY", 215 "SampleAfterValue": "100000", 216 "BriefDescription": "L2 lines alloacated" 217 }, 218 { 219 "EventCode": "0xF1", 220 "Counter": "0,1,2,3", 221 "UMask": "0x4", 222 "EventName": "L2_LINES_IN.E_STATE", 223 "SampleAfterValue": "100000", 224 "BriefDescription": "L2 lines allocated in the E state" 225 }, 226 { 227 "EventCode": "0xF1", 228 "Counter": "0,1,2,3", 229 "UMask": "0x2", 230 "EventName": "L2_LINES_IN.S_STATE", 231 "SampleAfterValue": "100000", 232 "BriefDescription": "L2 lines allocated in the S state" 233 }, 234 { 235 "EventCode": "0xF2", 236 "Counter": "0,1,2,3", 237 "UMask": "0xf", 238 "EventName": "L2_LINES_OUT.ANY", 239 "SampleAfterValue": "100000", 240 "BriefDescription": "L2 lines evicted" 241 }, 242 { 243 "EventCode": "0xF2", 244 "Counter": "0,1,2,3", 245 "UMask": "0x1", 246 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 247 "SampleAfterValue": "100000", 248 "BriefDescription": "L2 lines evicted by a demand request" 249 }, 250 { 251 "EventCode": "0xF2", 252 "Counter": "0,1,2,3", 253 "UMask": "0x2", 254 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 255 "SampleAfterValue": "100000", 256 "BriefDescription": "L2 modified lines evicted by a demand request" 257 }, 258 { 259 "EventCode": "0xF2", 260 "Counter": "0,1,2,3", 261 "UMask": "0x4", 262 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 263 "SampleAfterValue": "100000", 264 "BriefDescription": "L2 lines evicted by a prefetch request" 265 }, 266 { 267 "EventCode": "0xF2", 268 "Counter": "0,1,2,3", 269 "UMask": "0x8", 270 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 271 "SampleAfterValue": "100000", 272 "BriefDescription": "L2 modified lines evicted by a prefetch request" 273 }, 274 { 275 "EventCode": "0x24", 276 "Counter": "0,1,2,3", 277 "UMask": "0x10", 278 "EventName": "L2_RQSTS.IFETCH_HIT", 279 "SampleAfterValue": "200000", 280 "BriefDescription": "L2 instruction fetch hits" 281 }, 282 { 283 "EventCode": "0x24", 284 "Counter": "0,1,2,3", 285 "UMask": "0x20", 286 "EventName": "L2_RQSTS.IFETCH_MISS", 287 "SampleAfterValue": "200000", 288 "BriefDescription": "L2 instruction fetch misses" 289 }, 290 { 291 "EventCode": "0x24", 292 "Counter": "0,1,2,3", 293 "UMask": "0x30", 294 "EventName": "L2_RQSTS.IFETCHES", 295 "SampleAfterValue": "200000", 296 "BriefDescription": "L2 instruction fetches" 297 }, 298 { 299 "EventCode": "0x24", 300 "Counter": "0,1,2,3", 301 "UMask": "0x1", 302 "EventName": "L2_RQSTS.LD_HIT", 303 "SampleAfterValue": "200000", 304 "BriefDescription": "L2 load hits" 305 }, 306 { 307 "EventCode": "0x24", 308 "Counter": "0,1,2,3", 309 "UMask": "0x2", 310 "EventName": "L2_RQSTS.LD_MISS", 311 "SampleAfterValue": "200000", 312 "BriefDescription": "L2 load misses" 313 }, 314 { 315 "EventCode": "0x24", 316 "Counter": "0,1,2,3", 317 "UMask": "0x3", 318 "EventName": "L2_RQSTS.LOADS", 319 "SampleAfterValue": "200000", 320 "BriefDescription": "L2 requests" 321 }, 322 { 323 "EventCode": "0x24", 324 "Counter": "0,1,2,3", 325 "UMask": "0xaa", 326 "EventName": "L2_RQSTS.MISS", 327 "SampleAfterValue": "200000", 328 "BriefDescription": "All L2 misses" 329 }, 330 { 331 "EventCode": "0x24", 332 "Counter": "0,1,2,3", 333 "UMask": "0x40", 334 "EventName": "L2_RQSTS.PREFETCH_HIT", 335 "SampleAfterValue": "200000", 336 "BriefDescription": "L2 prefetch hits" 337 }, 338 { 339 "EventCode": "0x24", 340 "Counter": "0,1,2,3", 341 "UMask": "0x80", 342 "EventName": "L2_RQSTS.PREFETCH_MISS", 343 "SampleAfterValue": "200000", 344 "BriefDescription": "L2 prefetch misses" 345 }, 346 { 347 "EventCode": "0x24", 348 "Counter": "0,1,2,3", 349 "UMask": "0xc0", 350 "EventName": "L2_RQSTS.PREFETCHES", 351 "SampleAfterValue": "200000", 352 "BriefDescription": "All L2 prefetches" 353 }, 354 { 355 "EventCode": "0x24", 356 "Counter": "0,1,2,3", 357 "UMask": "0xff", 358 "EventName": "L2_RQSTS.REFERENCES", 359 "SampleAfterValue": "200000", 360 "BriefDescription": "All L2 requests" 361 }, 362 { 363 "EventCode": "0x24", 364 "Counter": "0,1,2,3", 365 "UMask": "0x4", 366 "EventName": "L2_RQSTS.RFO_HIT", 367 "SampleAfterValue": "200000", 368 "BriefDescription": "L2 RFO hits" 369 }, 370 { 371 "EventCode": "0x24", 372 "Counter": "0,1,2,3", 373 "UMask": "0x8", 374 "EventName": "L2_RQSTS.RFO_MISS", 375 "SampleAfterValue": "200000", 376 "BriefDescription": "L2 RFO misses" 377 }, 378 { 379 "EventCode": "0x24", 380 "Counter": "0,1,2,3", 381 "UMask": "0xc", 382 "EventName": "L2_RQSTS.RFOS", 383 "SampleAfterValue": "200000", 384 "BriefDescription": "L2 RFO requests" 385 }, 386 { 387 "EventCode": "0xF0", 388 "Counter": "0,1,2,3", 389 "UMask": "0x80", 390 "EventName": "L2_TRANSACTIONS.ANY", 391 "SampleAfterValue": "200000", 392 "BriefDescription": "All L2 transactions" 393 }, 394 { 395 "EventCode": "0xF0", 396 "Counter": "0,1,2,3", 397 "UMask": "0x20", 398 "EventName": "L2_TRANSACTIONS.FILL", 399 "SampleAfterValue": "200000", 400 "BriefDescription": "L2 fill transactions" 401 }, 402 { 403 "EventCode": "0xF0", 404 "Counter": "0,1,2,3", 405 "UMask": "0x4", 406 "EventName": "L2_TRANSACTIONS.IFETCH", 407 "SampleAfterValue": "200000", 408 "BriefDescription": "L2 instruction fetch transactions" 409 }, 410 { 411 "EventCode": "0xF0", 412 "Counter": "0,1,2,3", 413 "UMask": "0x10", 414 "EventName": "L2_TRANSACTIONS.L1D_WB", 415 "SampleAfterValue": "200000", 416 "BriefDescription": "L1D writeback to L2 transactions" 417 }, 418 { 419 "EventCode": "0xF0", 420 "Counter": "0,1,2,3", 421 "UMask": "0x1", 422 "EventName": "L2_TRANSACTIONS.LOAD", 423 "SampleAfterValue": "200000", 424 "BriefDescription": "L2 Load transactions" 425 }, 426 { 427 "EventCode": "0xF0", 428 "Counter": "0,1,2,3", 429 "UMask": "0x8", 430 "EventName": "L2_TRANSACTIONS.PREFETCH", 431 "SampleAfterValue": "200000", 432 "BriefDescription": "L2 prefetch transactions" 433 }, 434 { 435 "EventCode": "0xF0", 436 "Counter": "0,1,2,3", 437 "UMask": "0x2", 438 "EventName": "L2_TRANSACTIONS.RFO", 439 "SampleAfterValue": "200000", 440 "BriefDescription": "L2 RFO transactions" 441 }, 442 { 443 "EventCode": "0xF0", 444 "Counter": "0,1,2,3", 445 "UMask": "0x40", 446 "EventName": "L2_TRANSACTIONS.WB", 447 "SampleAfterValue": "200000", 448 "BriefDescription": "L2 writeback to LLC transactions" 449 }, 450 { 451 "EventCode": "0x27", 452 "Counter": "0,1,2,3", 453 "UMask": "0x40", 454 "EventName": "L2_WRITE.LOCK.E_STATE", 455 "SampleAfterValue": "100000", 456 "BriefDescription": "L2 demand lock RFOs in E state" 457 }, 458 { 459 "EventCode": "0x27", 460 "Counter": "0,1,2,3", 461 "UMask": "0xe0", 462 "EventName": "L2_WRITE.LOCK.HIT", 463 "SampleAfterValue": "100000", 464 "BriefDescription": "All demand L2 lock RFOs that hit the cache" 465 }, 466 { 467 "EventCode": "0x27", 468 "Counter": "0,1,2,3", 469 "UMask": "0x10", 470 "EventName": "L2_WRITE.LOCK.I_STATE", 471 "SampleAfterValue": "100000", 472 "BriefDescription": "L2 demand lock RFOs in I state (misses)" 473 }, 474 { 475 "EventCode": "0x27", 476 "Counter": "0,1,2,3", 477 "UMask": "0x80", 478 "EventName": "L2_WRITE.LOCK.M_STATE", 479 "SampleAfterValue": "100000", 480 "BriefDescription": "L2 demand lock RFOs in M state" 481 }, 482 { 483 "EventCode": "0x27", 484 "Counter": "0,1,2,3", 485 "UMask": "0xf0", 486 "EventName": "L2_WRITE.LOCK.MESI", 487 "SampleAfterValue": "100000", 488 "BriefDescription": "All demand L2 lock RFOs" 489 }, 490 { 491 "EventCode": "0x27", 492 "Counter": "0,1,2,3", 493 "UMask": "0x20", 494 "EventName": "L2_WRITE.LOCK.S_STATE", 495 "SampleAfterValue": "100000", 496 "BriefDescription": "L2 demand lock RFOs in S state" 497 }, 498 { 499 "EventCode": "0x27", 500 "Counter": "0,1,2,3", 501 "UMask": "0xe", 502 "EventName": "L2_WRITE.RFO.HIT", 503 "SampleAfterValue": "100000", 504 "BriefDescription": "All L2 demand store RFOs that hit the cache" 505 }, 506 { 507 "EventCode": "0x27", 508 "Counter": "0,1,2,3", 509 "UMask": "0x1", 510 "EventName": "L2_WRITE.RFO.I_STATE", 511 "SampleAfterValue": "100000", 512 "BriefDescription": "L2 demand store RFOs in I state (misses)" 513 }, 514 { 515 "EventCode": "0x27", 516 "Counter": "0,1,2,3", 517 "UMask": "0x8", 518 "EventName": "L2_WRITE.RFO.M_STATE", 519 "SampleAfterValue": "100000", 520 "BriefDescription": "L2 demand store RFOs in M state" 521 }, 522 { 523 "EventCode": "0x27", 524 "Counter": "0,1,2,3", 525 "UMask": "0xf", 526 "EventName": "L2_WRITE.RFO.MESI", 527 "SampleAfterValue": "100000", 528 "BriefDescription": "All L2 demand store RFOs" 529 }, 530 { 531 "EventCode": "0x27", 532 "Counter": "0,1,2,3", 533 "UMask": "0x2", 534 "EventName": "L2_WRITE.RFO.S_STATE", 535 "SampleAfterValue": "100000", 536 "BriefDescription": "L2 demand store RFOs in S state" 537 }, 538 { 539 "EventCode": "0x2E", 540 "Counter": "0,1,2,3", 541 "UMask": "0x41", 542 "EventName": "LONGEST_LAT_CACHE.MISS", 543 "SampleAfterValue": "100000", 544 "BriefDescription": "Longest latency cache miss" 545 }, 546 { 547 "EventCode": "0x2E", 548 "Counter": "0,1,2,3", 549 "UMask": "0x4f", 550 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 551 "SampleAfterValue": "200000", 552 "BriefDescription": "Longest latency cache reference" 553 }, 554 { 555 "PEBS": "1", 556 "EventCode": "0xB", 557 "Counter": "0,1,2,3", 558 "UMask": "0x1", 559 "EventName": "MEM_INST_RETIRED.LOADS", 560 "SampleAfterValue": "2000000", 561 "BriefDescription": "Instructions retired which contains a load (Precise Event)" 562 }, 563 { 564 "PEBS": "1", 565 "EventCode": "0xB", 566 "Counter": "0,1,2,3", 567 "UMask": "0x2", 568 "EventName": "MEM_INST_RETIRED.STORES", 569 "SampleAfterValue": "2000000", 570 "BriefDescription": "Instructions retired which contains a store (Precise Event)" 571 }, 572 { 573 "PEBS": "1", 574 "EventCode": "0xCB", 575 "Counter": "0,1,2,3", 576 "UMask": "0x40", 577 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 578 "SampleAfterValue": "200000", 579 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" 580 }, 581 { 582 "PEBS": "1", 583 "EventCode": "0xCB", 584 "Counter": "0,1,2,3", 585 "UMask": "0x1", 586 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 587 "SampleAfterValue": "2000000", 588 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" 589 }, 590 { 591 "PEBS": "1", 592 "EventCode": "0xCB", 593 "Counter": "0,1,2,3", 594 "UMask": "0x2", 595 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 596 "SampleAfterValue": "200000", 597 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" 598 }, 599 { 600 "PEBS": "1", 601 "EventCode": "0xCB", 602 "Counter": "0,1,2,3", 603 "UMask": "0x10", 604 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 605 "SampleAfterValue": "10000", 606 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" 607 }, 608 { 609 "PEBS": "1", 610 "EventCode": "0xCB", 611 "Counter": "0,1,2,3", 612 "UMask": "0x4", 613 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 614 "SampleAfterValue": "40000", 615 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" 616 }, 617 { 618 "PEBS": "1", 619 "EventCode": "0xCB", 620 "Counter": "0,1,2,3", 621 "UMask": "0x8", 622 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 623 "SampleAfterValue": "40000", 624 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" 625 }, 626 { 627 "PEBS": "1", 628 "EventCode": "0xF", 629 "Counter": "0,1,2,3", 630 "UMask": "0x2", 631 "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", 632 "SampleAfterValue": "40000", 633 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)" 634 }, 635 { 636 "PEBS": "1", 637 "EventCode": "0xF", 638 "Counter": "0,1,2,3", 639 "UMask": "0x8", 640 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 641 "SampleAfterValue": "20000", 642 "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)" 643 }, 644 { 645 "PEBS": "1", 646 "EventCode": "0xF", 647 "Counter": "0,1,2,3", 648 "UMask": "0x20", 649 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", 650 "SampleAfterValue": "10000", 651 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)" 652 }, 653 { 654 "PEBS": "1", 655 "EventCode": "0xF", 656 "Counter": "0,1,2,3", 657 "UMask": "0x80", 658 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", 659 "SampleAfterValue": "4000", 660 "BriefDescription": "Load instructions retired IO (Precise Event)" 661 }, 662 { 663 "PEBS": "1", 664 "EventCode": "0xF", 665 "Counter": "0,1,2,3", 666 "UMask": "0x4", 667 "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM", 668 "SampleAfterValue": "40000", 669 "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)" 670 }, 671 { 672 "EventCode": "0xB0", 673 "Counter": "0,1,2,3", 674 "UMask": "0x80", 675 "EventName": "OFFCORE_REQUESTS.ANY", 676 "SampleAfterValue": "100000", 677 "BriefDescription": "All offcore requests" 678 }, 679 { 680 "EventCode": "0xB0", 681 "Counter": "0,1,2,3", 682 "UMask": "0x8", 683 "EventName": "OFFCORE_REQUESTS.ANY.READ", 684 "SampleAfterValue": "100000", 685 "BriefDescription": "Offcore read requests" 686 }, 687 { 688 "EventCode": "0xB0", 689 "Counter": "0,1,2,3", 690 "UMask": "0x10", 691 "EventName": "OFFCORE_REQUESTS.ANY.RFO", 692 "SampleAfterValue": "100000", 693 "BriefDescription": "Offcore RFO requests" 694 }, 695 { 696 "EventCode": "0xB0", 697 "Counter": "0,1,2,3", 698 "UMask": "0x2", 699 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", 700 "SampleAfterValue": "100000", 701 "BriefDescription": "Offcore demand code read requests" 702 }, 703 { 704 "EventCode": "0xB0", 705 "Counter": "0,1,2,3", 706 "UMask": "0x1", 707 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", 708 "SampleAfterValue": "100000", 709 "BriefDescription": "Offcore demand data read requests" 710 }, 711 { 712 "EventCode": "0xB0", 713 "Counter": "0,1,2,3", 714 "UMask": "0x4", 715 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", 716 "SampleAfterValue": "100000", 717 "BriefDescription": "Offcore demand RFO requests" 718 }, 719 { 720 "EventCode": "0xB0", 721 "Counter": "0,1,2,3", 722 "UMask": "0x40", 723 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 724 "SampleAfterValue": "100000", 725 "BriefDescription": "Offcore L1 data cache writebacks" 726 }, 727 { 728 "EventCode": "0x60", 729 "UMask": "0x8", 730 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", 731 "SampleAfterValue": "2000000", 732 "BriefDescription": "Outstanding offcore reads" 733 }, 734 { 735 "EventCode": "0x60", 736 "UMask": "0x8", 737 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", 738 "SampleAfterValue": "2000000", 739 "BriefDescription": "Cycles offcore reads busy", 740 "CounterMask": "1" 741 }, 742 { 743 "EventCode": "0x60", 744 "UMask": "0x2", 745 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", 746 "SampleAfterValue": "2000000", 747 "BriefDescription": "Outstanding offcore demand code reads" 748 }, 749 { 750 "EventCode": "0x60", 751 "UMask": "0x2", 752 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", 753 "SampleAfterValue": "2000000", 754 "BriefDescription": "Cycles offcore demand code read busy", 755 "CounterMask": "1" 756 }, 757 { 758 "EventCode": "0x60", 759 "UMask": "0x1", 760 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", 761 "SampleAfterValue": "2000000", 762 "BriefDescription": "Outstanding offcore demand data reads" 763 }, 764 { 765 "EventCode": "0x60", 766 "UMask": "0x1", 767 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", 768 "SampleAfterValue": "2000000", 769 "BriefDescription": "Cycles offcore demand data read busy", 770 "CounterMask": "1" 771 }, 772 { 773 "EventCode": "0x60", 774 "UMask": "0x4", 775 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", 776 "SampleAfterValue": "2000000", 777 "BriefDescription": "Outstanding offcore demand RFOs" 778 }, 779 { 780 "EventCode": "0x60", 781 "UMask": "0x4", 782 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", 783 "SampleAfterValue": "2000000", 784 "BriefDescription": "Cycles offcore demand RFOs busy", 785 "CounterMask": "1" 786 }, 787 { 788 "EventCode": "0xB2", 789 "Counter": "0,1,2,3", 790 "UMask": "0x1", 791 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 792 "SampleAfterValue": "100000", 793 "BriefDescription": "Offcore requests blocked due to Super Queue full" 794 }, 795 { 796 "EventCode": "0xF4", 797 "Counter": "0,1,2,3", 798 "UMask": "0x4", 799 "EventName": "SQ_MISC.LRU_HINTS", 800 "SampleAfterValue": "2000000", 801 "BriefDescription": "Super Queue LRU hints sent to LLC" 802 }, 803 { 804 "EventCode": "0xF4", 805 "Counter": "0,1,2,3", 806 "UMask": "0x10", 807 "EventName": "SQ_MISC.SPLIT_LOCK", 808 "SampleAfterValue": "2000000", 809 "BriefDescription": "Super Queue lock splits across a cache line" 810 }, 811 { 812 "EventCode": "0x6", 813 "Counter": "0,1,2,3", 814 "UMask": "0x4", 815 "EventName": "STORE_BLOCKS.AT_RET", 816 "SampleAfterValue": "200000", 817 "BriefDescription": "Loads delayed with at-Retirement block code" 818 }, 819 { 820 "EventCode": "0x6", 821 "Counter": "0,1,2,3", 822 "UMask": "0x8", 823 "EventName": "STORE_BLOCKS.L1D_BLOCK", 824 "SampleAfterValue": "200000", 825 "BriefDescription": "Cacheable loads delayed with L1D block code" 826 }, 827 { 828 "PEBS": "2", 829 "EventCode": "0xB", 830 "MSRValue": "0x0", 831 "Counter": "3", 832 "UMask": "0x10", 833 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 834 "MSRIndex": "0x3F6", 835 "SampleAfterValue": "2000000", 836 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" 837 }, 838 { 839 "PEBS": "2", 840 "EventCode": "0xB", 841 "MSRValue": "0x400", 842 "Counter": "3", 843 "UMask": "0x10", 844 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 845 "MSRIndex": "0x3F6", 846 "SampleAfterValue": "100", 847 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" 848 }, 849 { 850 "PEBS": "2", 851 "EventCode": "0xB", 852 "MSRValue": "0x80", 853 "Counter": "3", 854 "UMask": "0x10", 855 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 856 "MSRIndex": "0x3F6", 857 "SampleAfterValue": "1000", 858 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" 859 }, 860 { 861 "PEBS": "2", 862 "EventCode": "0xB", 863 "MSRValue": "0x10", 864 "Counter": "3", 865 "UMask": "0x10", 866 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 867 "MSRIndex": "0x3F6", 868 "SampleAfterValue": "10000", 869 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" 870 }, 871 { 872 "PEBS": "2", 873 "EventCode": "0xB", 874 "MSRValue": "0x4000", 875 "Counter": "3", 876 "UMask": "0x10", 877 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 878 "MSRIndex": "0x3F6", 879 "SampleAfterValue": "5", 880 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" 881 }, 882 { 883 "PEBS": "2", 884 "EventCode": "0xB", 885 "MSRValue": "0x800", 886 "Counter": "3", 887 "UMask": "0x10", 888 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 889 "MSRIndex": "0x3F6", 890 "SampleAfterValue": "50", 891 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" 892 }, 893 { 894 "PEBS": "2", 895 "EventCode": "0xB", 896 "MSRValue": "0x100", 897 "Counter": "3", 898 "UMask": "0x10", 899 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 900 "MSRIndex": "0x3F6", 901 "SampleAfterValue": "500", 902 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" 903 }, 904 { 905 "PEBS": "2", 906 "EventCode": "0xB", 907 "MSRValue": "0x20", 908 "Counter": "3", 909 "UMask": "0x10", 910 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 911 "MSRIndex": "0x3F6", 912 "SampleAfterValue": "5000", 913 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" 914 }, 915 { 916 "PEBS": "2", 917 "EventCode": "0xB", 918 "MSRValue": "0x8000", 919 "Counter": "3", 920 "UMask": "0x10", 921 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 922 "MSRIndex": "0x3F6", 923 "SampleAfterValue": "3", 924 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" 925 }, 926 { 927 "PEBS": "2", 928 "EventCode": "0xB", 929 "MSRValue": "0x4", 930 "Counter": "3", 931 "UMask": "0x10", 932 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 933 "MSRIndex": "0x3F6", 934 "SampleAfterValue": "50000", 935 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" 936 }, 937 { 938 "PEBS": "2", 939 "EventCode": "0xB", 940 "MSRValue": "0x1000", 941 "Counter": "3", 942 "UMask": "0x10", 943 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 944 "MSRIndex": "0x3F6", 945 "SampleAfterValue": "20", 946 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" 947 }, 948 { 949 "PEBS": "2", 950 "EventCode": "0xB", 951 "MSRValue": "0x200", 952 "Counter": "3", 953 "UMask": "0x10", 954 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 955 "MSRIndex": "0x3F6", 956 "SampleAfterValue": "200", 957 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" 958 }, 959 { 960 "PEBS": "2", 961 "EventCode": "0xB", 962 "MSRValue": "0x40", 963 "Counter": "3", 964 "UMask": "0x10", 965 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 966 "MSRIndex": "0x3F6", 967 "SampleAfterValue": "2000", 968 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" 969 }, 970 { 971 "PEBS": "2", 972 "EventCode": "0xB", 973 "MSRValue": "0x8", 974 "Counter": "3", 975 "UMask": "0x10", 976 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 977 "MSRIndex": "0x3F6", 978 "SampleAfterValue": "20000", 979 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" 980 }, 981 { 982 "PEBS": "2", 983 "EventCode": "0xB", 984 "MSRValue": "0x2000", 985 "Counter": "3", 986 "UMask": "0x10", 987 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 988 "MSRIndex": "0x3F6", 989 "SampleAfterValue": "10", 990 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" 991 }, 992 { 993 "EventCode": "0xB7", 994 "MSRValue": "0x7F11", 995 "Counter": "2", 996 "UMask": "0x1", 997 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 998 "MSRIndex": "0x1A6", 999 "SampleAfterValue": "100000", 1000 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 1001 "Offcore": "1" 1002 }, 1003 { 1004 "EventCode": "0xB7", 1005 "MSRValue": "0xFF11", 1006 "Counter": "2", 1007 "UMask": "0x1", 1008 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 1009 "MSRIndex": "0x1A6", 1010 "SampleAfterValue": "100000", 1011 "BriefDescription": "All offcore data reads", 1012 "Offcore": "1" 1013 }, 1014 { 1015 "EventCode": "0xB7", 1016 "MSRValue": "0x8011", 1017 "Counter": "2", 1018 "UMask": "0x1", 1019 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 1020 "MSRIndex": "0x1A6", 1021 "SampleAfterValue": "100000", 1022 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 1023 "Offcore": "1" 1024 }, 1025 { 1026 "EventCode": "0xB7", 1027 "MSRValue": "0x111", 1028 "Counter": "2", 1029 "UMask": "0x1", 1030 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 1031 "MSRIndex": "0x1A6", 1032 "SampleAfterValue": "100000", 1033 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 1034 "Offcore": "1" 1035 }, 1036 { 1037 "EventCode": "0xB7", 1038 "MSRValue": "0x211", 1039 "Counter": "2", 1040 "UMask": "0x1", 1041 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1042 "MSRIndex": "0x1A6", 1043 "SampleAfterValue": "100000", 1044 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 1045 "Offcore": "1" 1046 }, 1047 { 1048 "EventCode": "0xB7", 1049 "MSRValue": "0x411", 1050 "Counter": "2", 1051 "UMask": "0x1", 1052 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1053 "MSRIndex": "0x1A6", 1054 "SampleAfterValue": "100000", 1055 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 1056 "Offcore": "1" 1057 }, 1058 { 1059 "EventCode": "0xB7", 1060 "MSRValue": "0x711", 1061 "Counter": "2", 1062 "UMask": "0x1", 1063 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1064 "MSRIndex": "0x1A6", 1065 "SampleAfterValue": "100000", 1066 "BriefDescription": "Offcore data reads satisfied by the LLC", 1067 "Offcore": "1" 1068 }, 1069 { 1070 "EventCode": "0xB7", 1071 "MSRValue": "0x4711", 1072 "Counter": "2", 1073 "UMask": "0x1", 1074 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1075 "MSRIndex": "0x1A6", 1076 "SampleAfterValue": "100000", 1077 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 1078 "Offcore": "1" 1079 }, 1080 { 1081 "EventCode": "0xB7", 1082 "MSRValue": "0x1811", 1083 "Counter": "2", 1084 "UMask": "0x1", 1085 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1086 "MSRIndex": "0x1A6", 1087 "SampleAfterValue": "100000", 1088 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1089 "Offcore": "1" 1090 }, 1091 { 1092 "EventCode": "0xB7", 1093 "MSRValue": "0x3811", 1094 "Counter": "2", 1095 "UMask": "0x1", 1096 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1097 "MSRIndex": "0x1A6", 1098 "SampleAfterValue": "100000", 1099 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1100 "Offcore": "1" 1101 }, 1102 { 1103 "EventCode": "0xB7", 1104 "MSRValue": "0x1011", 1105 "Counter": "2", 1106 "UMask": "0x1", 1107 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1108 "MSRIndex": "0x1A6", 1109 "SampleAfterValue": "100000", 1110 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1111 "Offcore": "1" 1112 }, 1113 { 1114 "EventCode": "0xB7", 1115 "MSRValue": "0x811", 1116 "Counter": "2", 1117 "UMask": "0x1", 1118 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1119 "MSRIndex": "0x1A6", 1120 "SampleAfterValue": "100000", 1121 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1122 "Offcore": "1" 1123 }, 1124 { 1125 "EventCode": "0xB7", 1126 "MSRValue": "0x7F44", 1127 "Counter": "2", 1128 "UMask": "0x1", 1129 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1130 "MSRIndex": "0x1A6", 1131 "SampleAfterValue": "100000", 1132 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1133 "Offcore": "1" 1134 }, 1135 { 1136 "EventCode": "0xB7", 1137 "MSRValue": "0xFF44", 1138 "Counter": "2", 1139 "UMask": "0x1", 1140 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1141 "MSRIndex": "0x1A6", 1142 "SampleAfterValue": "100000", 1143 "BriefDescription": "All offcore code reads", 1144 "Offcore": "1" 1145 }, 1146 { 1147 "EventCode": "0xB7", 1148 "MSRValue": "0x8044", 1149 "Counter": "2", 1150 "UMask": "0x1", 1151 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1152 "MSRIndex": "0x1A6", 1153 "SampleAfterValue": "100000", 1154 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1155 "Offcore": "1" 1156 }, 1157 { 1158 "EventCode": "0xB7", 1159 "MSRValue": "0x144", 1160 "Counter": "2", 1161 "UMask": "0x1", 1162 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1163 "MSRIndex": "0x1A6", 1164 "SampleAfterValue": "100000", 1165 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1166 "Offcore": "1" 1167 }, 1168 { 1169 "EventCode": "0xB7", 1170 "MSRValue": "0x244", 1171 "Counter": "2", 1172 "UMask": "0x1", 1173 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1174 "MSRIndex": "0x1A6", 1175 "SampleAfterValue": "100000", 1176 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1177 "Offcore": "1" 1178 }, 1179 { 1180 "EventCode": "0xB7", 1181 "MSRValue": "0x444", 1182 "Counter": "2", 1183 "UMask": "0x1", 1184 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1185 "MSRIndex": "0x1A6", 1186 "SampleAfterValue": "100000", 1187 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1188 "Offcore": "1" 1189 }, 1190 { 1191 "EventCode": "0xB7", 1192 "MSRValue": "0x744", 1193 "Counter": "2", 1194 "UMask": "0x1", 1195 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1196 "MSRIndex": "0x1A6", 1197 "SampleAfterValue": "100000", 1198 "BriefDescription": "Offcore code reads satisfied by the LLC", 1199 "Offcore": "1" 1200 }, 1201 { 1202 "EventCode": "0xB7", 1203 "MSRValue": "0x4744", 1204 "Counter": "2", 1205 "UMask": "0x1", 1206 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1207 "MSRIndex": "0x1A6", 1208 "SampleAfterValue": "100000", 1209 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1210 "Offcore": "1" 1211 }, 1212 { 1213 "EventCode": "0xB7", 1214 "MSRValue": "0x1844", 1215 "Counter": "2", 1216 "UMask": "0x1", 1217 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1218 "MSRIndex": "0x1A6", 1219 "SampleAfterValue": "100000", 1220 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1221 "Offcore": "1" 1222 }, 1223 { 1224 "EventCode": "0xB7", 1225 "MSRValue": "0x3844", 1226 "Counter": "2", 1227 "UMask": "0x1", 1228 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1229 "MSRIndex": "0x1A6", 1230 "SampleAfterValue": "100000", 1231 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1232 "Offcore": "1" 1233 }, 1234 { 1235 "EventCode": "0xB7", 1236 "MSRValue": "0x1044", 1237 "Counter": "2", 1238 "UMask": "0x1", 1239 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1240 "MSRIndex": "0x1A6", 1241 "SampleAfterValue": "100000", 1242 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1243 "Offcore": "1" 1244 }, 1245 { 1246 "EventCode": "0xB7", 1247 "MSRValue": "0x844", 1248 "Counter": "2", 1249 "UMask": "0x1", 1250 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1251 "MSRIndex": "0x1A6", 1252 "SampleAfterValue": "100000", 1253 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1254 "Offcore": "1" 1255 }, 1256 { 1257 "EventCode": "0xB7", 1258 "MSRValue": "0x7FFF", 1259 "Counter": "2", 1260 "UMask": "0x1", 1261 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1262 "MSRIndex": "0x1A6", 1263 "SampleAfterValue": "100000", 1264 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1265 "Offcore": "1" 1266 }, 1267 { 1268 "EventCode": "0xB7", 1269 "MSRValue": "0xFFFF", 1270 "Counter": "2", 1271 "UMask": "0x1", 1272 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1273 "MSRIndex": "0x1A6", 1274 "SampleAfterValue": "100000", 1275 "BriefDescription": "All offcore requests", 1276 "Offcore": "1" 1277 }, 1278 { 1279 "EventCode": "0xB7", 1280 "MSRValue": "0x80FF", 1281 "Counter": "2", 1282 "UMask": "0x1", 1283 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1284 "MSRIndex": "0x1A6", 1285 "SampleAfterValue": "100000", 1286 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1287 "Offcore": "1" 1288 }, 1289 { 1290 "EventCode": "0xB7", 1291 "MSRValue": "0x1FF", 1292 "Counter": "2", 1293 "UMask": "0x1", 1294 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1295 "MSRIndex": "0x1A6", 1296 "SampleAfterValue": "100000", 1297 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1298 "Offcore": "1" 1299 }, 1300 { 1301 "EventCode": "0xB7", 1302 "MSRValue": "0x2FF", 1303 "Counter": "2", 1304 "UMask": "0x1", 1305 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1306 "MSRIndex": "0x1A6", 1307 "SampleAfterValue": "100000", 1308 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1309 "Offcore": "1" 1310 }, 1311 { 1312 "EventCode": "0xB7", 1313 "MSRValue": "0x4FF", 1314 "Counter": "2", 1315 "UMask": "0x1", 1316 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1317 "MSRIndex": "0x1A6", 1318 "SampleAfterValue": "100000", 1319 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1320 "Offcore": "1" 1321 }, 1322 { 1323 "EventCode": "0xB7", 1324 "MSRValue": "0x7FF", 1325 "Counter": "2", 1326 "UMask": "0x1", 1327 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1328 "MSRIndex": "0x1A6", 1329 "SampleAfterValue": "100000", 1330 "BriefDescription": "Offcore requests satisfied by the LLC", 1331 "Offcore": "1" 1332 }, 1333 { 1334 "EventCode": "0xB7", 1335 "MSRValue": "0x47FF", 1336 "Counter": "2", 1337 "UMask": "0x1", 1338 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1339 "MSRIndex": "0x1A6", 1340 "SampleAfterValue": "100000", 1341 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1342 "Offcore": "1" 1343 }, 1344 { 1345 "EventCode": "0xB7", 1346 "MSRValue": "0x18FF", 1347 "Counter": "2", 1348 "UMask": "0x1", 1349 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1350 "MSRIndex": "0x1A6", 1351 "SampleAfterValue": "100000", 1352 "BriefDescription": "Offcore requests satisfied by a remote cache", 1353 "Offcore": "1" 1354 }, 1355 { 1356 "EventCode": "0xB7", 1357 "MSRValue": "0x38FF", 1358 "Counter": "2", 1359 "UMask": "0x1", 1360 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1361 "MSRIndex": "0x1A6", 1362 "SampleAfterValue": "100000", 1363 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1364 "Offcore": "1" 1365 }, 1366 { 1367 "EventCode": "0xB7", 1368 "MSRValue": "0x10FF", 1369 "Counter": "2", 1370 "UMask": "0x1", 1371 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1372 "MSRIndex": "0x1A6", 1373 "SampleAfterValue": "100000", 1374 "BriefDescription": "Offcore requests that HIT in a remote cache", 1375 "Offcore": "1" 1376 }, 1377 { 1378 "EventCode": "0xB7", 1379 "MSRValue": "0x8FF", 1380 "Counter": "2", 1381 "UMask": "0x1", 1382 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1383 "MSRIndex": "0x1A6", 1384 "SampleAfterValue": "100000", 1385 "BriefDescription": "Offcore requests that HITM in a remote cache", 1386 "Offcore": "1" 1387 }, 1388 { 1389 "EventCode": "0xB7", 1390 "MSRValue": "0x7F22", 1391 "Counter": "2", 1392 "UMask": "0x1", 1393 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1394 "MSRIndex": "0x1A6", 1395 "SampleAfterValue": "100000", 1396 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1397 "Offcore": "1" 1398 }, 1399 { 1400 "EventCode": "0xB7", 1401 "MSRValue": "0xFF22", 1402 "Counter": "2", 1403 "UMask": "0x1", 1404 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1405 "MSRIndex": "0x1A6", 1406 "SampleAfterValue": "100000", 1407 "BriefDescription": "All offcore RFO requests", 1408 "Offcore": "1" 1409 }, 1410 { 1411 "EventCode": "0xB7", 1412 "MSRValue": "0x8022", 1413 "Counter": "2", 1414 "UMask": "0x1", 1415 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1416 "MSRIndex": "0x1A6", 1417 "SampleAfterValue": "100000", 1418 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1419 "Offcore": "1" 1420 }, 1421 { 1422 "EventCode": "0xB7", 1423 "MSRValue": "0x122", 1424 "Counter": "2", 1425 "UMask": "0x1", 1426 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1427 "MSRIndex": "0x1A6", 1428 "SampleAfterValue": "100000", 1429 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1430 "Offcore": "1" 1431 }, 1432 { 1433 "EventCode": "0xB7", 1434 "MSRValue": "0x222", 1435 "Counter": "2", 1436 "UMask": "0x1", 1437 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1438 "MSRIndex": "0x1A6", 1439 "SampleAfterValue": "100000", 1440 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1441 "Offcore": "1" 1442 }, 1443 { 1444 "EventCode": "0xB7", 1445 "MSRValue": "0x422", 1446 "Counter": "2", 1447 "UMask": "0x1", 1448 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1449 "MSRIndex": "0x1A6", 1450 "SampleAfterValue": "100000", 1451 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1452 "Offcore": "1" 1453 }, 1454 { 1455 "EventCode": "0xB7", 1456 "MSRValue": "0x722", 1457 "Counter": "2", 1458 "UMask": "0x1", 1459 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1460 "MSRIndex": "0x1A6", 1461 "SampleAfterValue": "100000", 1462 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1463 "Offcore": "1" 1464 }, 1465 { 1466 "EventCode": "0xB7", 1467 "MSRValue": "0x4722", 1468 "Counter": "2", 1469 "UMask": "0x1", 1470 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1471 "MSRIndex": "0x1A6", 1472 "SampleAfterValue": "100000", 1473 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1474 "Offcore": "1" 1475 }, 1476 { 1477 "EventCode": "0xB7", 1478 "MSRValue": "0x1822", 1479 "Counter": "2", 1480 "UMask": "0x1", 1481 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1482 "MSRIndex": "0x1A6", 1483 "SampleAfterValue": "100000", 1484 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1485 "Offcore": "1" 1486 }, 1487 { 1488 "EventCode": "0xB7", 1489 "MSRValue": "0x3822", 1490 "Counter": "2", 1491 "UMask": "0x1", 1492 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1493 "MSRIndex": "0x1A6", 1494 "SampleAfterValue": "100000", 1495 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1496 "Offcore": "1" 1497 }, 1498 { 1499 "EventCode": "0xB7", 1500 "MSRValue": "0x1022", 1501 "Counter": "2", 1502 "UMask": "0x1", 1503 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1504 "MSRIndex": "0x1A6", 1505 "SampleAfterValue": "100000", 1506 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1507 "Offcore": "1" 1508 }, 1509 { 1510 "EventCode": "0xB7", 1511 "MSRValue": "0x822", 1512 "Counter": "2", 1513 "UMask": "0x1", 1514 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1515 "MSRIndex": "0x1A6", 1516 "SampleAfterValue": "100000", 1517 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1518 "Offcore": "1" 1519 }, 1520 { 1521 "EventCode": "0xB7", 1522 "MSRValue": "0x7F08", 1523 "Counter": "2", 1524 "UMask": "0x1", 1525 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1526 "MSRIndex": "0x1A6", 1527 "SampleAfterValue": "100000", 1528 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1529 "Offcore": "1" 1530 }, 1531 { 1532 "EventCode": "0xB7", 1533 "MSRValue": "0xFF08", 1534 "Counter": "2", 1535 "UMask": "0x1", 1536 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1537 "MSRIndex": "0x1A6", 1538 "SampleAfterValue": "100000", 1539 "BriefDescription": "All offcore writebacks", 1540 "Offcore": "1" 1541 }, 1542 { 1543 "EventCode": "0xB7", 1544 "MSRValue": "0x8008", 1545 "Counter": "2", 1546 "UMask": "0x1", 1547 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1548 "MSRIndex": "0x1A6", 1549 "SampleAfterValue": "100000", 1550 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1551 "Offcore": "1" 1552 }, 1553 { 1554 "EventCode": "0xB7", 1555 "MSRValue": "0x108", 1556 "Counter": "2", 1557 "UMask": "0x1", 1558 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1559 "MSRIndex": "0x1A6", 1560 "SampleAfterValue": "100000", 1561 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1562 "Offcore": "1" 1563 }, 1564 { 1565 "EventCode": "0xB7", 1566 "MSRValue": "0x408", 1567 "Counter": "2", 1568 "UMask": "0x1", 1569 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1570 "MSRIndex": "0x1A6", 1571 "SampleAfterValue": "100000", 1572 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1573 "Offcore": "1" 1574 }, 1575 { 1576 "EventCode": "0xB7", 1577 "MSRValue": "0x708", 1578 "Counter": "2", 1579 "UMask": "0x1", 1580 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1581 "MSRIndex": "0x1A6", 1582 "SampleAfterValue": "100000", 1583 "BriefDescription": "Offcore writebacks to the LLC", 1584 "Offcore": "1" 1585 }, 1586 { 1587 "EventCode": "0xB7", 1588 "MSRValue": "0x4708", 1589 "Counter": "2", 1590 "UMask": "0x1", 1591 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1592 "MSRIndex": "0x1A6", 1593 "SampleAfterValue": "100000", 1594 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1595 "Offcore": "1" 1596 }, 1597 { 1598 "EventCode": "0xB7", 1599 "MSRValue": "0x1808", 1600 "Counter": "2", 1601 "UMask": "0x1", 1602 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1603 "MSRIndex": "0x1A6", 1604 "SampleAfterValue": "100000", 1605 "BriefDescription": "Offcore writebacks to a remote cache", 1606 "Offcore": "1" 1607 }, 1608 { 1609 "EventCode": "0xB7", 1610 "MSRValue": "0x3808", 1611 "Counter": "2", 1612 "UMask": "0x1", 1613 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1614 "MSRIndex": "0x1A6", 1615 "SampleAfterValue": "100000", 1616 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1617 "Offcore": "1" 1618 }, 1619 { 1620 "EventCode": "0xB7", 1621 "MSRValue": "0x1008", 1622 "Counter": "2", 1623 "UMask": "0x1", 1624 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1625 "MSRIndex": "0x1A6", 1626 "SampleAfterValue": "100000", 1627 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1628 "Offcore": "1" 1629 }, 1630 { 1631 "EventCode": "0xB7", 1632 "MSRValue": "0x808", 1633 "Counter": "2", 1634 "UMask": "0x1", 1635 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1636 "MSRIndex": "0x1A6", 1637 "SampleAfterValue": "100000", 1638 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1639 "Offcore": "1" 1640 }, 1641 { 1642 "EventCode": "0xB7", 1643 "MSRValue": "0x7F77", 1644 "Counter": "2", 1645 "UMask": "0x1", 1646 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1647 "MSRIndex": "0x1A6", 1648 "SampleAfterValue": "100000", 1649 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1650 "Offcore": "1" 1651 }, 1652 { 1653 "EventCode": "0xB7", 1654 "MSRValue": "0xFF77", 1655 "Counter": "2", 1656 "UMask": "0x1", 1657 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1658 "MSRIndex": "0x1A6", 1659 "SampleAfterValue": "100000", 1660 "BriefDescription": "All offcore code or data read requests", 1661 "Offcore": "1" 1662 }, 1663 { 1664 "EventCode": "0xB7", 1665 "MSRValue": "0x8077", 1666 "Counter": "2", 1667 "UMask": "0x1", 1668 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1669 "MSRIndex": "0x1A6", 1670 "SampleAfterValue": "100000", 1671 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1672 "Offcore": "1" 1673 }, 1674 { 1675 "EventCode": "0xB7", 1676 "MSRValue": "0x177", 1677 "Counter": "2", 1678 "UMask": "0x1", 1679 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1680 "MSRIndex": "0x1A6", 1681 "SampleAfterValue": "100000", 1682 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1683 "Offcore": "1" 1684 }, 1685 { 1686 "EventCode": "0xB7", 1687 "MSRValue": "0x277", 1688 "Counter": "2", 1689 "UMask": "0x1", 1690 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1691 "MSRIndex": "0x1A6", 1692 "SampleAfterValue": "100000", 1693 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1694 "Offcore": "1" 1695 }, 1696 { 1697 "EventCode": "0xB7", 1698 "MSRValue": "0x477", 1699 "Counter": "2", 1700 "UMask": "0x1", 1701 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1702 "MSRIndex": "0x1A6", 1703 "SampleAfterValue": "100000", 1704 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1705 "Offcore": "1" 1706 }, 1707 { 1708 "EventCode": "0xB7", 1709 "MSRValue": "0x777", 1710 "Counter": "2", 1711 "UMask": "0x1", 1712 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1713 "MSRIndex": "0x1A6", 1714 "SampleAfterValue": "100000", 1715 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1716 "Offcore": "1" 1717 }, 1718 { 1719 "EventCode": "0xB7", 1720 "MSRValue": "0x4777", 1721 "Counter": "2", 1722 "UMask": "0x1", 1723 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1724 "MSRIndex": "0x1A6", 1725 "SampleAfterValue": "100000", 1726 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1727 "Offcore": "1" 1728 }, 1729 { 1730 "EventCode": "0xB7", 1731 "MSRValue": "0x1877", 1732 "Counter": "2", 1733 "UMask": "0x1", 1734 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1735 "MSRIndex": "0x1A6", 1736 "SampleAfterValue": "100000", 1737 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1738 "Offcore": "1" 1739 }, 1740 { 1741 "EventCode": "0xB7", 1742 "MSRValue": "0x3877", 1743 "Counter": "2", 1744 "UMask": "0x1", 1745 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1746 "MSRIndex": "0x1A6", 1747 "SampleAfterValue": "100000", 1748 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1749 "Offcore": "1" 1750 }, 1751 { 1752 "EventCode": "0xB7", 1753 "MSRValue": "0x1077", 1754 "Counter": "2", 1755 "UMask": "0x1", 1756 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1757 "MSRIndex": "0x1A6", 1758 "SampleAfterValue": "100000", 1759 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1760 "Offcore": "1" 1761 }, 1762 { 1763 "EventCode": "0xB7", 1764 "MSRValue": "0x877", 1765 "Counter": "2", 1766 "UMask": "0x1", 1767 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1768 "MSRIndex": "0x1A6", 1769 "SampleAfterValue": "100000", 1770 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1771 "Offcore": "1" 1772 }, 1773 { 1774 "EventCode": "0xB7", 1775 "MSRValue": "0x7F33", 1776 "Counter": "2", 1777 "UMask": "0x1", 1778 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1779 "MSRIndex": "0x1A6", 1780 "SampleAfterValue": "100000", 1781 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1782 "Offcore": "1" 1783 }, 1784 { 1785 "EventCode": "0xB7", 1786 "MSRValue": "0xFF33", 1787 "Counter": "2", 1788 "UMask": "0x1", 1789 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1790 "MSRIndex": "0x1A6", 1791 "SampleAfterValue": "100000", 1792 "BriefDescription": "Offcore request = all data, response = any location", 1793 "Offcore": "1" 1794 }, 1795 { 1796 "EventCode": "0xB7", 1797 "MSRValue": "0x8033", 1798 "Counter": "2", 1799 "UMask": "0x1", 1800 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1801 "MSRIndex": "0x1A6", 1802 "SampleAfterValue": "100000", 1803 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", 1804 "Offcore": "1" 1805 }, 1806 { 1807 "EventCode": "0xB7", 1808 "MSRValue": "0x133", 1809 "Counter": "2", 1810 "UMask": "0x1", 1811 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1812 "MSRIndex": "0x1A6", 1813 "SampleAfterValue": "100000", 1814 "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", 1815 "Offcore": "1" 1816 }, 1817 { 1818 "EventCode": "0xB7", 1819 "MSRValue": "0x233", 1820 "Counter": "2", 1821 "UMask": "0x1", 1822 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1823 "MSRIndex": "0x1A6", 1824 "SampleAfterValue": "100000", 1825 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", 1826 "Offcore": "1" 1827 }, 1828 { 1829 "EventCode": "0xB7", 1830 "MSRValue": "0x433", 1831 "Counter": "2", 1832 "UMask": "0x1", 1833 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1834 "MSRIndex": "0x1A6", 1835 "SampleAfterValue": "100000", 1836 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", 1837 "Offcore": "1" 1838 }, 1839 { 1840 "EventCode": "0xB7", 1841 "MSRValue": "0x733", 1842 "Counter": "2", 1843 "UMask": "0x1", 1844 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1845 "MSRIndex": "0x1A6", 1846 "SampleAfterValue": "100000", 1847 "BriefDescription": "Offcore request = all data, response = local cache", 1848 "Offcore": "1" 1849 }, 1850 { 1851 "EventCode": "0xB7", 1852 "MSRValue": "0x4733", 1853 "Counter": "2", 1854 "UMask": "0x1", 1855 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1856 "MSRIndex": "0x1A6", 1857 "SampleAfterValue": "100000", 1858 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1859 "Offcore": "1" 1860 }, 1861 { 1862 "EventCode": "0xB7", 1863 "MSRValue": "0x1833", 1864 "Counter": "2", 1865 "UMask": "0x1", 1866 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1867 "MSRIndex": "0x1A6", 1868 "SampleAfterValue": "100000", 1869 "BriefDescription": "Offcore request = all data, response = remote cache", 1870 "Offcore": "1" 1871 }, 1872 { 1873 "EventCode": "0xB7", 1874 "MSRValue": "0x3833", 1875 "Counter": "2", 1876 "UMask": "0x1", 1877 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1878 "MSRIndex": "0x1A6", 1879 "SampleAfterValue": "100000", 1880 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1881 "Offcore": "1" 1882 }, 1883 { 1884 "EventCode": "0xB7", 1885 "MSRValue": "0x1033", 1886 "Counter": "2", 1887 "UMask": "0x1", 1888 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1889 "MSRIndex": "0x1A6", 1890 "SampleAfterValue": "100000", 1891 "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", 1892 "Offcore": "1" 1893 }, 1894 { 1895 "EventCode": "0xB7", 1896 "MSRValue": "0x833", 1897 "Counter": "2", 1898 "UMask": "0x1", 1899 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1900 "MSRIndex": "0x1A6", 1901 "SampleAfterValue": "100000", 1902 "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", 1903 "Offcore": "1" 1904 }, 1905 { 1906 "EventCode": "0xB7", 1907 "MSRValue": "0x7F03", 1908 "Counter": "2", 1909 "UMask": "0x1", 1910 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1911 "MSRIndex": "0x1A6", 1912 "SampleAfterValue": "100000", 1913 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1914 "Offcore": "1" 1915 }, 1916 { 1917 "EventCode": "0xB7", 1918 "MSRValue": "0xFF03", 1919 "Counter": "2", 1920 "UMask": "0x1", 1921 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1922 "MSRIndex": "0x1A6", 1923 "SampleAfterValue": "100000", 1924 "BriefDescription": "All offcore demand data requests", 1925 "Offcore": "1" 1926 }, 1927 { 1928 "EventCode": "0xB7", 1929 "MSRValue": "0x8003", 1930 "Counter": "2", 1931 "UMask": "0x1", 1932 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1933 "MSRIndex": "0x1A6", 1934 "SampleAfterValue": "100000", 1935 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1936 "Offcore": "1" 1937 }, 1938 { 1939 "EventCode": "0xB7", 1940 "MSRValue": "0x103", 1941 "Counter": "2", 1942 "UMask": "0x1", 1943 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1944 "MSRIndex": "0x1A6", 1945 "SampleAfterValue": "100000", 1946 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1947 "Offcore": "1" 1948 }, 1949 { 1950 "EventCode": "0xB7", 1951 "MSRValue": "0x203", 1952 "Counter": "2", 1953 "UMask": "0x1", 1954 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1955 "MSRIndex": "0x1A6", 1956 "SampleAfterValue": "100000", 1957 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1958 "Offcore": "1" 1959 }, 1960 { 1961 "EventCode": "0xB7", 1962 "MSRValue": "0x403", 1963 "Counter": "2", 1964 "UMask": "0x1", 1965 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1966 "MSRIndex": "0x1A6", 1967 "SampleAfterValue": "100000", 1968 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1969 "Offcore": "1" 1970 }, 1971 { 1972 "EventCode": "0xB7", 1973 "MSRValue": "0x703", 1974 "Counter": "2", 1975 "UMask": "0x1", 1976 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1977 "MSRIndex": "0x1A6", 1978 "SampleAfterValue": "100000", 1979 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1980 "Offcore": "1" 1981 }, 1982 { 1983 "EventCode": "0xB7", 1984 "MSRValue": "0x4703", 1985 "Counter": "2", 1986 "UMask": "0x1", 1987 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1988 "MSRIndex": "0x1A6", 1989 "SampleAfterValue": "100000", 1990 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1991 "Offcore": "1" 1992 }, 1993 { 1994 "EventCode": "0xB7", 1995 "MSRValue": "0x1803", 1996 "Counter": "2", 1997 "UMask": "0x1", 1998 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1999 "MSRIndex": "0x1A6", 2000 "SampleAfterValue": "100000", 2001 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 2002 "Offcore": "1" 2003 }, 2004 { 2005 "EventCode": "0xB7", 2006 "MSRValue": "0x3803", 2007 "Counter": "2", 2008 "UMask": "0x1", 2009 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 2010 "MSRIndex": "0x1A6", 2011 "SampleAfterValue": "100000", 2012 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 2013 "Offcore": "1" 2014 }, 2015 { 2016 "EventCode": "0xB7", 2017 "MSRValue": "0x1003", 2018 "Counter": "2", 2019 "UMask": "0x1", 2020 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 2021 "MSRIndex": "0x1A6", 2022 "SampleAfterValue": "100000", 2023 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 2024 "Offcore": "1" 2025 }, 2026 { 2027 "EventCode": "0xB7", 2028 "MSRValue": "0x803", 2029 "Counter": "2", 2030 "UMask": "0x1", 2031 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 2032 "MSRIndex": "0x1A6", 2033 "SampleAfterValue": "100000", 2034 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 2035 "Offcore": "1" 2036 }, 2037 { 2038 "EventCode": "0xB7", 2039 "MSRValue": "0x7F01", 2040 "Counter": "2", 2041 "UMask": "0x1", 2042 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 2043 "MSRIndex": "0x1A6", 2044 "SampleAfterValue": "100000", 2045 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 2046 "Offcore": "1" 2047 }, 2048 { 2049 "EventCode": "0xB7", 2050 "MSRValue": "0xFF01", 2051 "Counter": "2", 2052 "UMask": "0x1", 2053 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 2054 "MSRIndex": "0x1A6", 2055 "SampleAfterValue": "100000", 2056 "BriefDescription": "All offcore demand data reads", 2057 "Offcore": "1" 2058 }, 2059 { 2060 "EventCode": "0xB7", 2061 "MSRValue": "0x8001", 2062 "Counter": "2", 2063 "UMask": "0x1", 2064 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 2065 "MSRIndex": "0x1A6", 2066 "SampleAfterValue": "100000", 2067 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 2068 "Offcore": "1" 2069 }, 2070 { 2071 "EventCode": "0xB7", 2072 "MSRValue": "0x101", 2073 "Counter": "2", 2074 "UMask": "0x1", 2075 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2076 "MSRIndex": "0x1A6", 2077 "SampleAfterValue": "100000", 2078 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 2079 "Offcore": "1" 2080 }, 2081 { 2082 "EventCode": "0xB7", 2083 "MSRValue": "0x201", 2084 "Counter": "2", 2085 "UMask": "0x1", 2086 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2087 "MSRIndex": "0x1A6", 2088 "SampleAfterValue": "100000", 2089 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 2090 "Offcore": "1" 2091 }, 2092 { 2093 "EventCode": "0xB7", 2094 "MSRValue": "0x401", 2095 "Counter": "2", 2096 "UMask": "0x1", 2097 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2098 "MSRIndex": "0x1A6", 2099 "SampleAfterValue": "100000", 2100 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 2101 "Offcore": "1" 2102 }, 2103 { 2104 "EventCode": "0xB7", 2105 "MSRValue": "0x701", 2106 "Counter": "2", 2107 "UMask": "0x1", 2108 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 2109 "MSRIndex": "0x1A6", 2110 "SampleAfterValue": "100000", 2111 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 2112 "Offcore": "1" 2113 }, 2114 { 2115 "EventCode": "0xB7", 2116 "MSRValue": "0x4701", 2117 "Counter": "2", 2118 "UMask": "0x1", 2119 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 2120 "MSRIndex": "0x1A6", 2121 "SampleAfterValue": "100000", 2122 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 2123 "Offcore": "1" 2124 }, 2125 { 2126 "EventCode": "0xB7", 2127 "MSRValue": "0x1801", 2128 "Counter": "2", 2129 "UMask": "0x1", 2130 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 2131 "MSRIndex": "0x1A6", 2132 "SampleAfterValue": "100000", 2133 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 2134 "Offcore": "1" 2135 }, 2136 { 2137 "EventCode": "0xB7", 2138 "MSRValue": "0x3801", 2139 "Counter": "2", 2140 "UMask": "0x1", 2141 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 2142 "MSRIndex": "0x1A6", 2143 "SampleAfterValue": "100000", 2144 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 2145 "Offcore": "1" 2146 }, 2147 { 2148 "EventCode": "0xB7", 2149 "MSRValue": "0x1001", 2150 "Counter": "2", 2151 "UMask": "0x1", 2152 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 2153 "MSRIndex": "0x1A6", 2154 "SampleAfterValue": "100000", 2155 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 2156 "Offcore": "1" 2157 }, 2158 { 2159 "EventCode": "0xB7", 2160 "MSRValue": "0x801", 2161 "Counter": "2", 2162 "UMask": "0x1", 2163 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 2164 "MSRIndex": "0x1A6", 2165 "SampleAfterValue": "100000", 2166 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 2167 "Offcore": "1" 2168 }, 2169 { 2170 "EventCode": "0xB7", 2171 "MSRValue": "0x7F04", 2172 "Counter": "2", 2173 "UMask": "0x1", 2174 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2175 "MSRIndex": "0x1A6", 2176 "SampleAfterValue": "100000", 2177 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 2178 "Offcore": "1" 2179 }, 2180 { 2181 "EventCode": "0xB7", 2182 "MSRValue": "0xFF04", 2183 "Counter": "2", 2184 "UMask": "0x1", 2185 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2186 "MSRIndex": "0x1A6", 2187 "SampleAfterValue": "100000", 2188 "BriefDescription": "All offcore demand code reads", 2189 "Offcore": "1" 2190 }, 2191 { 2192 "EventCode": "0xB7", 2193 "MSRValue": "0x8004", 2194 "Counter": "2", 2195 "UMask": "0x1", 2196 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2197 "MSRIndex": "0x1A6", 2198 "SampleAfterValue": "100000", 2199 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2200 "Offcore": "1" 2201 }, 2202 { 2203 "EventCode": "0xB7", 2204 "MSRValue": "0x104", 2205 "Counter": "2", 2206 "UMask": "0x1", 2207 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2208 "MSRIndex": "0x1A6", 2209 "SampleAfterValue": "100000", 2210 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2211 "Offcore": "1" 2212 }, 2213 { 2214 "EventCode": "0xB7", 2215 "MSRValue": "0x204", 2216 "Counter": "2", 2217 "UMask": "0x1", 2218 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2219 "MSRIndex": "0x1A6", 2220 "SampleAfterValue": "100000", 2221 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2222 "Offcore": "1" 2223 }, 2224 { 2225 "EventCode": "0xB7", 2226 "MSRValue": "0x404", 2227 "Counter": "2", 2228 "UMask": "0x1", 2229 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2230 "MSRIndex": "0x1A6", 2231 "SampleAfterValue": "100000", 2232 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2233 "Offcore": "1" 2234 }, 2235 { 2236 "EventCode": "0xB7", 2237 "MSRValue": "0x704", 2238 "Counter": "2", 2239 "UMask": "0x1", 2240 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2241 "MSRIndex": "0x1A6", 2242 "SampleAfterValue": "100000", 2243 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2244 "Offcore": "1" 2245 }, 2246 { 2247 "EventCode": "0xB7", 2248 "MSRValue": "0x4704", 2249 "Counter": "2", 2250 "UMask": "0x1", 2251 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2252 "MSRIndex": "0x1A6", 2253 "SampleAfterValue": "100000", 2254 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2255 "Offcore": "1" 2256 }, 2257 { 2258 "EventCode": "0xB7", 2259 "MSRValue": "0x1804", 2260 "Counter": "2", 2261 "UMask": "0x1", 2262 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2263 "MSRIndex": "0x1A6", 2264 "SampleAfterValue": "100000", 2265 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2266 "Offcore": "1" 2267 }, 2268 { 2269 "EventCode": "0xB7", 2270 "MSRValue": "0x3804", 2271 "Counter": "2", 2272 "UMask": "0x1", 2273 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2274 "MSRIndex": "0x1A6", 2275 "SampleAfterValue": "100000", 2276 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2277 "Offcore": "1" 2278 }, 2279 { 2280 "EventCode": "0xB7", 2281 "MSRValue": "0x1004", 2282 "Counter": "2", 2283 "UMask": "0x1", 2284 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2285 "MSRIndex": "0x1A6", 2286 "SampleAfterValue": "100000", 2287 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2288 "Offcore": "1" 2289 }, 2290 { 2291 "EventCode": "0xB7", 2292 "MSRValue": "0x804", 2293 "Counter": "2", 2294 "UMask": "0x1", 2295 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2296 "MSRIndex": "0x1A6", 2297 "SampleAfterValue": "100000", 2298 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2299 "Offcore": "1" 2300 }, 2301 { 2302 "EventCode": "0xB7", 2303 "MSRValue": "0x7F02", 2304 "Counter": "2", 2305 "UMask": "0x1", 2306 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2307 "MSRIndex": "0x1A6", 2308 "SampleAfterValue": "100000", 2309 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2310 "Offcore": "1" 2311 }, 2312 { 2313 "EventCode": "0xB7", 2314 "MSRValue": "0xFF02", 2315 "Counter": "2", 2316 "UMask": "0x1", 2317 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2318 "MSRIndex": "0x1A6", 2319 "SampleAfterValue": "100000", 2320 "BriefDescription": "All offcore demand RFO requests", 2321 "Offcore": "1" 2322 }, 2323 { 2324 "EventCode": "0xB7", 2325 "MSRValue": "0x8002", 2326 "Counter": "2", 2327 "UMask": "0x1", 2328 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2329 "MSRIndex": "0x1A6", 2330 "SampleAfterValue": "100000", 2331 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2332 "Offcore": "1" 2333 }, 2334 { 2335 "EventCode": "0xB7", 2336 "MSRValue": "0x102", 2337 "Counter": "2", 2338 "UMask": "0x1", 2339 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2340 "MSRIndex": "0x1A6", 2341 "SampleAfterValue": "100000", 2342 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2343 "Offcore": "1" 2344 }, 2345 { 2346 "EventCode": "0xB7", 2347 "MSRValue": "0x202", 2348 "Counter": "2", 2349 "UMask": "0x1", 2350 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2351 "MSRIndex": "0x1A6", 2352 "SampleAfterValue": "100000", 2353 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2354 "Offcore": "1" 2355 }, 2356 { 2357 "EventCode": "0xB7", 2358 "MSRValue": "0x402", 2359 "Counter": "2", 2360 "UMask": "0x1", 2361 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2362 "MSRIndex": "0x1A6", 2363 "SampleAfterValue": "100000", 2364 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2365 "Offcore": "1" 2366 }, 2367 { 2368 "EventCode": "0xB7", 2369 "MSRValue": "0x702", 2370 "Counter": "2", 2371 "UMask": "0x1", 2372 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2373 "MSRIndex": "0x1A6", 2374 "SampleAfterValue": "100000", 2375 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2376 "Offcore": "1" 2377 }, 2378 { 2379 "EventCode": "0xB7", 2380 "MSRValue": "0x4702", 2381 "Counter": "2", 2382 "UMask": "0x1", 2383 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2384 "MSRIndex": "0x1A6", 2385 "SampleAfterValue": "100000", 2386 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2387 "Offcore": "1" 2388 }, 2389 { 2390 "EventCode": "0xB7", 2391 "MSRValue": "0x1802", 2392 "Counter": "2", 2393 "UMask": "0x1", 2394 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2395 "MSRIndex": "0x1A6", 2396 "SampleAfterValue": "100000", 2397 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2398 "Offcore": "1" 2399 }, 2400 { 2401 "EventCode": "0xB7", 2402 "MSRValue": "0x3802", 2403 "Counter": "2", 2404 "UMask": "0x1", 2405 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2406 "MSRIndex": "0x1A6", 2407 "SampleAfterValue": "100000", 2408 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2409 "Offcore": "1" 2410 }, 2411 { 2412 "EventCode": "0xB7", 2413 "MSRValue": "0x1002", 2414 "Counter": "2", 2415 "UMask": "0x1", 2416 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2417 "MSRIndex": "0x1A6", 2418 "SampleAfterValue": "100000", 2419 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2420 "Offcore": "1" 2421 }, 2422 { 2423 "EventCode": "0xB7", 2424 "MSRValue": "0x802", 2425 "Counter": "2", 2426 "UMask": "0x1", 2427 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2428 "MSRIndex": "0x1A6", 2429 "SampleAfterValue": "100000", 2430 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2431 "Offcore": "1" 2432 }, 2433 { 2434 "EventCode": "0xB7", 2435 "MSRValue": "0x7F80", 2436 "Counter": "2", 2437 "UMask": "0x1", 2438 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2439 "MSRIndex": "0x1A6", 2440 "SampleAfterValue": "100000", 2441 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2442 "Offcore": "1" 2443 }, 2444 { 2445 "EventCode": "0xB7", 2446 "MSRValue": "0xFF80", 2447 "Counter": "2", 2448 "UMask": "0x1", 2449 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2450 "MSRIndex": "0x1A6", 2451 "SampleAfterValue": "100000", 2452 "BriefDescription": "All offcore other requests", 2453 "Offcore": "1" 2454 }, 2455 { 2456 "EventCode": "0xB7", 2457 "MSRValue": "0x8080", 2458 "Counter": "2", 2459 "UMask": "0x1", 2460 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2461 "MSRIndex": "0x1A6", 2462 "SampleAfterValue": "100000", 2463 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2464 "Offcore": "1" 2465 }, 2466 { 2467 "EventCode": "0xB7", 2468 "MSRValue": "0x180", 2469 "Counter": "2", 2470 "UMask": "0x1", 2471 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2472 "MSRIndex": "0x1A6", 2473 "SampleAfterValue": "100000", 2474 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2475 "Offcore": "1" 2476 }, 2477 { 2478 "EventCode": "0xB7", 2479 "MSRValue": "0x280", 2480 "Counter": "2", 2481 "UMask": "0x1", 2482 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2483 "MSRIndex": "0x1A6", 2484 "SampleAfterValue": "100000", 2485 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2486 "Offcore": "1" 2487 }, 2488 { 2489 "EventCode": "0xB7", 2490 "MSRValue": "0x480", 2491 "Counter": "2", 2492 "UMask": "0x1", 2493 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2494 "MSRIndex": "0x1A6", 2495 "SampleAfterValue": "100000", 2496 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2497 "Offcore": "1" 2498 }, 2499 { 2500 "EventCode": "0xB7", 2501 "MSRValue": "0x780", 2502 "Counter": "2", 2503 "UMask": "0x1", 2504 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2505 "MSRIndex": "0x1A6", 2506 "SampleAfterValue": "100000", 2507 "BriefDescription": "Offcore other requests satisfied by the LLC", 2508 "Offcore": "1" 2509 }, 2510 { 2511 "EventCode": "0xB7", 2512 "MSRValue": "0x4780", 2513 "Counter": "2", 2514 "UMask": "0x1", 2515 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2516 "MSRIndex": "0x1A6", 2517 "SampleAfterValue": "100000", 2518 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2519 "Offcore": "1" 2520 }, 2521 { 2522 "EventCode": "0xB7", 2523 "MSRValue": "0x1880", 2524 "Counter": "2", 2525 "UMask": "0x1", 2526 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2527 "MSRIndex": "0x1A6", 2528 "SampleAfterValue": "100000", 2529 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2530 "Offcore": "1" 2531 }, 2532 { 2533 "EventCode": "0xB7", 2534 "MSRValue": "0x3880", 2535 "Counter": "2", 2536 "UMask": "0x1", 2537 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2538 "MSRIndex": "0x1A6", 2539 "SampleAfterValue": "100000", 2540 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2541 "Offcore": "1" 2542 }, 2543 { 2544 "EventCode": "0xB7", 2545 "MSRValue": "0x1080", 2546 "Counter": "2", 2547 "UMask": "0x1", 2548 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2549 "MSRIndex": "0x1A6", 2550 "SampleAfterValue": "100000", 2551 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2552 "Offcore": "1" 2553 }, 2554 { 2555 "EventCode": "0xB7", 2556 "MSRValue": "0x880", 2557 "Counter": "2", 2558 "UMask": "0x1", 2559 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2560 "MSRIndex": "0x1A6", 2561 "SampleAfterValue": "100000", 2562 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2563 "Offcore": "1" 2564 }, 2565 { 2566 "EventCode": "0xB7", 2567 "MSRValue": "0x7F30", 2568 "Counter": "2", 2569 "UMask": "0x1", 2570 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2571 "MSRIndex": "0x1A6", 2572 "SampleAfterValue": "100000", 2573 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2574 "Offcore": "1" 2575 }, 2576 { 2577 "EventCode": "0xB7", 2578 "MSRValue": "0xFF30", 2579 "Counter": "2", 2580 "UMask": "0x1", 2581 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2582 "MSRIndex": "0x1A6", 2583 "SampleAfterValue": "100000", 2584 "BriefDescription": "All offcore prefetch data requests", 2585 "Offcore": "1" 2586 }, 2587 { 2588 "EventCode": "0xB7", 2589 "MSRValue": "0x8030", 2590 "Counter": "2", 2591 "UMask": "0x1", 2592 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2593 "MSRIndex": "0x1A6", 2594 "SampleAfterValue": "100000", 2595 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2596 "Offcore": "1" 2597 }, 2598 { 2599 "EventCode": "0xB7", 2600 "MSRValue": "0x130", 2601 "Counter": "2", 2602 "UMask": "0x1", 2603 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2604 "MSRIndex": "0x1A6", 2605 "SampleAfterValue": "100000", 2606 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2607 "Offcore": "1" 2608 }, 2609 { 2610 "EventCode": "0xB7", 2611 "MSRValue": "0x230", 2612 "Counter": "2", 2613 "UMask": "0x1", 2614 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2615 "MSRIndex": "0x1A6", 2616 "SampleAfterValue": "100000", 2617 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2618 "Offcore": "1" 2619 }, 2620 { 2621 "EventCode": "0xB7", 2622 "MSRValue": "0x430", 2623 "Counter": "2", 2624 "UMask": "0x1", 2625 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2626 "MSRIndex": "0x1A6", 2627 "SampleAfterValue": "100000", 2628 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2629 "Offcore": "1" 2630 }, 2631 { 2632 "EventCode": "0xB7", 2633 "MSRValue": "0x730", 2634 "Counter": "2", 2635 "UMask": "0x1", 2636 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2637 "MSRIndex": "0x1A6", 2638 "SampleAfterValue": "100000", 2639 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2640 "Offcore": "1" 2641 }, 2642 { 2643 "EventCode": "0xB7", 2644 "MSRValue": "0x4730", 2645 "Counter": "2", 2646 "UMask": "0x1", 2647 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2648 "MSRIndex": "0x1A6", 2649 "SampleAfterValue": "100000", 2650 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2651 "Offcore": "1" 2652 }, 2653 { 2654 "EventCode": "0xB7", 2655 "MSRValue": "0x1830", 2656 "Counter": "2", 2657 "UMask": "0x1", 2658 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2659 "MSRIndex": "0x1A6", 2660 "SampleAfterValue": "100000", 2661 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2662 "Offcore": "1" 2663 }, 2664 { 2665 "EventCode": "0xB7", 2666 "MSRValue": "0x3830", 2667 "Counter": "2", 2668 "UMask": "0x1", 2669 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2670 "MSRIndex": "0x1A6", 2671 "SampleAfterValue": "100000", 2672 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2673 "Offcore": "1" 2674 }, 2675 { 2676 "EventCode": "0xB7", 2677 "MSRValue": "0x1030", 2678 "Counter": "2", 2679 "UMask": "0x1", 2680 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2681 "MSRIndex": "0x1A6", 2682 "SampleAfterValue": "100000", 2683 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2684 "Offcore": "1" 2685 }, 2686 { 2687 "EventCode": "0xB7", 2688 "MSRValue": "0x830", 2689 "Counter": "2", 2690 "UMask": "0x1", 2691 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2692 "MSRIndex": "0x1A6", 2693 "SampleAfterValue": "100000", 2694 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2695 "Offcore": "1" 2696 }, 2697 { 2698 "EventCode": "0xB7", 2699 "MSRValue": "0x7F10", 2700 "Counter": "2", 2701 "UMask": "0x1", 2702 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2703 "MSRIndex": "0x1A6", 2704 "SampleAfterValue": "100000", 2705 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2706 "Offcore": "1" 2707 }, 2708 { 2709 "EventCode": "0xB7", 2710 "MSRValue": "0xFF10", 2711 "Counter": "2", 2712 "UMask": "0x1", 2713 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2714 "MSRIndex": "0x1A6", 2715 "SampleAfterValue": "100000", 2716 "BriefDescription": "All offcore prefetch data reads", 2717 "Offcore": "1" 2718 }, 2719 { 2720 "EventCode": "0xB7", 2721 "MSRValue": "0x8010", 2722 "Counter": "2", 2723 "UMask": "0x1", 2724 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2725 "MSRIndex": "0x1A6", 2726 "SampleAfterValue": "100000", 2727 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2728 "Offcore": "1" 2729 }, 2730 { 2731 "EventCode": "0xB7", 2732 "MSRValue": "0x110", 2733 "Counter": "2", 2734 "UMask": "0x1", 2735 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2736 "MSRIndex": "0x1A6", 2737 "SampleAfterValue": "100000", 2738 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2739 "Offcore": "1" 2740 }, 2741 { 2742 "EventCode": "0xB7", 2743 "MSRValue": "0x210", 2744 "Counter": "2", 2745 "UMask": "0x1", 2746 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2747 "MSRIndex": "0x1A6", 2748 "SampleAfterValue": "100000", 2749 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2750 "Offcore": "1" 2751 }, 2752 { 2753 "EventCode": "0xB7", 2754 "MSRValue": "0x410", 2755 "Counter": "2", 2756 "UMask": "0x1", 2757 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2758 "MSRIndex": "0x1A6", 2759 "SampleAfterValue": "100000", 2760 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2761 "Offcore": "1" 2762 }, 2763 { 2764 "EventCode": "0xB7", 2765 "MSRValue": "0x710", 2766 "Counter": "2", 2767 "UMask": "0x1", 2768 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2769 "MSRIndex": "0x1A6", 2770 "SampleAfterValue": "100000", 2771 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2772 "Offcore": "1" 2773 }, 2774 { 2775 "EventCode": "0xB7", 2776 "MSRValue": "0x4710", 2777 "Counter": "2", 2778 "UMask": "0x1", 2779 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2780 "MSRIndex": "0x1A6", 2781 "SampleAfterValue": "100000", 2782 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2783 "Offcore": "1" 2784 }, 2785 { 2786 "EventCode": "0xB7", 2787 "MSRValue": "0x1810", 2788 "Counter": "2", 2789 "UMask": "0x1", 2790 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2791 "MSRIndex": "0x1A6", 2792 "SampleAfterValue": "100000", 2793 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2794 "Offcore": "1" 2795 }, 2796 { 2797 "EventCode": "0xB7", 2798 "MSRValue": "0x3810", 2799 "Counter": "2", 2800 "UMask": "0x1", 2801 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2802 "MSRIndex": "0x1A6", 2803 "SampleAfterValue": "100000", 2804 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2805 "Offcore": "1" 2806 }, 2807 { 2808 "EventCode": "0xB7", 2809 "MSRValue": "0x1010", 2810 "Counter": "2", 2811 "UMask": "0x1", 2812 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2813 "MSRIndex": "0x1A6", 2814 "SampleAfterValue": "100000", 2815 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2816 "Offcore": "1" 2817 }, 2818 { 2819 "EventCode": "0xB7", 2820 "MSRValue": "0x810", 2821 "Counter": "2", 2822 "UMask": "0x1", 2823 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2824 "MSRIndex": "0x1A6", 2825 "SampleAfterValue": "100000", 2826 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2827 "Offcore": "1" 2828 }, 2829 { 2830 "EventCode": "0xB7", 2831 "MSRValue": "0x7F40", 2832 "Counter": "2", 2833 "UMask": "0x1", 2834 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2835 "MSRIndex": "0x1A6", 2836 "SampleAfterValue": "100000", 2837 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2838 "Offcore": "1" 2839 }, 2840 { 2841 "EventCode": "0xB7", 2842 "MSRValue": "0xFF40", 2843 "Counter": "2", 2844 "UMask": "0x1", 2845 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2846 "MSRIndex": "0x1A6", 2847 "SampleAfterValue": "100000", 2848 "BriefDescription": "All offcore prefetch code reads", 2849 "Offcore": "1" 2850 }, 2851 { 2852 "EventCode": "0xB7", 2853 "MSRValue": "0x8040", 2854 "Counter": "2", 2855 "UMask": "0x1", 2856 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2857 "MSRIndex": "0x1A6", 2858 "SampleAfterValue": "100000", 2859 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2860 "Offcore": "1" 2861 }, 2862 { 2863 "EventCode": "0xB7", 2864 "MSRValue": "0x140", 2865 "Counter": "2", 2866 "UMask": "0x1", 2867 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2868 "MSRIndex": "0x1A6", 2869 "SampleAfterValue": "100000", 2870 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2871 "Offcore": "1" 2872 }, 2873 { 2874 "EventCode": "0xB7", 2875 "MSRValue": "0x240", 2876 "Counter": "2", 2877 "UMask": "0x1", 2878 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2879 "MSRIndex": "0x1A6", 2880 "SampleAfterValue": "100000", 2881 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2882 "Offcore": "1" 2883 }, 2884 { 2885 "EventCode": "0xB7", 2886 "MSRValue": "0x440", 2887 "Counter": "2", 2888 "UMask": "0x1", 2889 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2890 "MSRIndex": "0x1A6", 2891 "SampleAfterValue": "100000", 2892 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2893 "Offcore": "1" 2894 }, 2895 { 2896 "EventCode": "0xB7", 2897 "MSRValue": "0x740", 2898 "Counter": "2", 2899 "UMask": "0x1", 2900 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2901 "MSRIndex": "0x1A6", 2902 "SampleAfterValue": "100000", 2903 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2904 "Offcore": "1" 2905 }, 2906 { 2907 "EventCode": "0xB7", 2908 "MSRValue": "0x4740", 2909 "Counter": "2", 2910 "UMask": "0x1", 2911 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2912 "MSRIndex": "0x1A6", 2913 "SampleAfterValue": "100000", 2914 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2915 "Offcore": "1" 2916 }, 2917 { 2918 "EventCode": "0xB7", 2919 "MSRValue": "0x1840", 2920 "Counter": "2", 2921 "UMask": "0x1", 2922 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2923 "MSRIndex": "0x1A6", 2924 "SampleAfterValue": "100000", 2925 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2926 "Offcore": "1" 2927 }, 2928 { 2929 "EventCode": "0xB7", 2930 "MSRValue": "0x3840", 2931 "Counter": "2", 2932 "UMask": "0x1", 2933 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2934 "MSRIndex": "0x1A6", 2935 "SampleAfterValue": "100000", 2936 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2937 "Offcore": "1" 2938 }, 2939 { 2940 "EventCode": "0xB7", 2941 "MSRValue": "0x1040", 2942 "Counter": "2", 2943 "UMask": "0x1", 2944 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2945 "MSRIndex": "0x1A6", 2946 "SampleAfterValue": "100000", 2947 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2948 "Offcore": "1" 2949 }, 2950 { 2951 "EventCode": "0xB7", 2952 "MSRValue": "0x840", 2953 "Counter": "2", 2954 "UMask": "0x1", 2955 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2956 "MSRIndex": "0x1A6", 2957 "SampleAfterValue": "100000", 2958 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2959 "Offcore": "1" 2960 }, 2961 { 2962 "EventCode": "0xB7", 2963 "MSRValue": "0x7F20", 2964 "Counter": "2", 2965 "UMask": "0x1", 2966 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2967 "MSRIndex": "0x1A6", 2968 "SampleAfterValue": "100000", 2969 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2970 "Offcore": "1" 2971 }, 2972 { 2973 "EventCode": "0xB7", 2974 "MSRValue": "0xFF20", 2975 "Counter": "2", 2976 "UMask": "0x1", 2977 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2978 "MSRIndex": "0x1A6", 2979 "SampleAfterValue": "100000", 2980 "BriefDescription": "All offcore prefetch RFO requests", 2981 "Offcore": "1" 2982 }, 2983 { 2984 "EventCode": "0xB7", 2985 "MSRValue": "0x8020", 2986 "Counter": "2", 2987 "UMask": "0x1", 2988 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2989 "MSRIndex": "0x1A6", 2990 "SampleAfterValue": "100000", 2991 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2992 "Offcore": "1" 2993 }, 2994 { 2995 "EventCode": "0xB7", 2996 "MSRValue": "0x120", 2997 "Counter": "2", 2998 "UMask": "0x1", 2999 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 3000 "MSRIndex": "0x1A6", 3001 "SampleAfterValue": "100000", 3002 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 3003 "Offcore": "1" 3004 }, 3005 { 3006 "EventCode": "0xB7", 3007 "MSRValue": "0x220", 3008 "Counter": "2", 3009 "UMask": "0x1", 3010 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 3011 "MSRIndex": "0x1A6", 3012 "SampleAfterValue": "100000", 3013 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 3014 "Offcore": "1" 3015 }, 3016 { 3017 "EventCode": "0xB7", 3018 "MSRValue": "0x420", 3019 "Counter": "2", 3020 "UMask": "0x1", 3021 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 3022 "MSRIndex": "0x1A6", 3023 "SampleAfterValue": "100000", 3024 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 3025 "Offcore": "1" 3026 }, 3027 { 3028 "EventCode": "0xB7", 3029 "MSRValue": "0x720", 3030 "Counter": "2", 3031 "UMask": "0x1", 3032 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 3033 "MSRIndex": "0x1A6", 3034 "SampleAfterValue": "100000", 3035 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 3036 "Offcore": "1" 3037 }, 3038 { 3039 "EventCode": "0xB7", 3040 "MSRValue": "0x4720", 3041 "Counter": "2", 3042 "UMask": "0x1", 3043 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 3044 "MSRIndex": "0x1A6", 3045 "SampleAfterValue": "100000", 3046 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 3047 "Offcore": "1" 3048 }, 3049 { 3050 "EventCode": "0xB7", 3051 "MSRValue": "0x1820", 3052 "Counter": "2", 3053 "UMask": "0x1", 3054 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 3055 "MSRIndex": "0x1A6", 3056 "SampleAfterValue": "100000", 3057 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 3058 "Offcore": "1" 3059 }, 3060 { 3061 "EventCode": "0xB7", 3062 "MSRValue": "0x3820", 3063 "Counter": "2", 3064 "UMask": "0x1", 3065 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 3066 "MSRIndex": "0x1A6", 3067 "SampleAfterValue": "100000", 3068 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 3069 "Offcore": "1" 3070 }, 3071 { 3072 "EventCode": "0xB7", 3073 "MSRValue": "0x1020", 3074 "Counter": "2", 3075 "UMask": "0x1", 3076 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 3077 "MSRIndex": "0x1A6", 3078 "SampleAfterValue": "100000", 3079 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 3080 "Offcore": "1" 3081 }, 3082 { 3083 "EventCode": "0xB7", 3084 "MSRValue": "0x820", 3085 "Counter": "2", 3086 "UMask": "0x1", 3087 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 3088 "MSRIndex": "0x1A6", 3089 "SampleAfterValue": "100000", 3090 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 3091 "Offcore": "1" 3092 }, 3093 { 3094 "EventCode": "0xB7", 3095 "MSRValue": "0x7F70", 3096 "Counter": "2", 3097 "UMask": "0x1", 3098 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 3099 "MSRIndex": "0x1A6", 3100 "SampleAfterValue": "100000", 3101 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 3102 "Offcore": "1" 3103 }, 3104 { 3105 "EventCode": "0xB7", 3106 "MSRValue": "0xFF70", 3107 "Counter": "2", 3108 "UMask": "0x1", 3109 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 3110 "MSRIndex": "0x1A6", 3111 "SampleAfterValue": "100000", 3112 "BriefDescription": "All offcore prefetch requests", 3113 "Offcore": "1" 3114 }, 3115 { 3116 "EventCode": "0xB7", 3117 "MSRValue": "0x8070", 3118 "Counter": "2", 3119 "UMask": "0x1", 3120 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 3121 "MSRIndex": "0x1A6", 3122 "SampleAfterValue": "100000", 3123 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 3124 "Offcore": "1" 3125 }, 3126 { 3127 "EventCode": "0xB7", 3128 "MSRValue": "0x170", 3129 "Counter": "2", 3130 "UMask": "0x1", 3131 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 3132 "MSRIndex": "0x1A6", 3133 "SampleAfterValue": "100000", 3134 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 3135 "Offcore": "1" 3136 }, 3137 { 3138 "EventCode": "0xB7", 3139 "MSRValue": "0x270", 3140 "Counter": "2", 3141 "UMask": "0x1", 3142 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 3143 "MSRIndex": "0x1A6", 3144 "SampleAfterValue": "100000", 3145 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 3146 "Offcore": "1" 3147 }, 3148 { 3149 "EventCode": "0xB7", 3150 "MSRValue": "0x470", 3151 "Counter": "2", 3152 "UMask": "0x1", 3153 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 3154 "MSRIndex": "0x1A6", 3155 "SampleAfterValue": "100000", 3156 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 3157 "Offcore": "1" 3158 }, 3159 { 3160 "EventCode": "0xB7", 3161 "MSRValue": "0x770", 3162 "Counter": "2", 3163 "UMask": "0x1", 3164 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 3165 "MSRIndex": "0x1A6", 3166 "SampleAfterValue": "100000", 3167 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 3168 "Offcore": "1" 3169 }, 3170 { 3171 "EventCode": "0xB7", 3172 "MSRValue": "0x4770", 3173 "Counter": "2", 3174 "UMask": "0x1", 3175 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 3176 "MSRIndex": "0x1A6", 3177 "SampleAfterValue": "100000", 3178 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 3179 "Offcore": "1" 3180 }, 3181 { 3182 "EventCode": "0xB7", 3183 "MSRValue": "0x1870", 3184 "Counter": "2", 3185 "UMask": "0x1", 3186 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 3187 "MSRIndex": "0x1A6", 3188 "SampleAfterValue": "100000", 3189 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 3190 "Offcore": "1" 3191 }, 3192 { 3193 "EventCode": "0xB7", 3194 "MSRValue": "0x3870", 3195 "Counter": "2", 3196 "UMask": "0x1", 3197 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 3198 "MSRIndex": "0x1A6", 3199 "SampleAfterValue": "100000", 3200 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 3201 "Offcore": "1" 3202 }, 3203 { 3204 "EventCode": "0xB7", 3205 "MSRValue": "0x1070", 3206 "Counter": "2", 3207 "UMask": "0x1", 3208 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 3209 "MSRIndex": "0x1A6", 3210 "SampleAfterValue": "100000", 3211 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 3212 "Offcore": "1" 3213 }, 3214 { 3215 "EventCode": "0xB7", 3216 "MSRValue": "0x870", 3217 "Counter": "2", 3218 "UMask": "0x1", 3219 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 3220 "MSRIndex": "0x1A6", 3221 "SampleAfterValue": "100000", 3222 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 3223 "Offcore": "1" 3224 } 3225]