1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Device Tree file for LX2160AQDS
4//
5// Copyright 2018-2020 NXP
6
7/dts-v1/;
8
9#include "fsl-lx2160a.dtsi"
10
11/ {
12	model = "NXP Layerscape LX2160AQDS";
13	compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
14
15	aliases {
16		crypto = &crypto;
17		serial0 = &uart0;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	sb_3v3: regulator-sb3v3 {
25		compatible = "regulator-fixed";
26		regulator-name = "MC34717-3.3VSB";
27		regulator-min-microvolt = <3300000>;
28		regulator-max-microvolt = <3300000>;
29		regulator-boot-on;
30		regulator-always-on;
31	};
32
33	mdio-mux-1 {
34		compatible = "mdio-mux-multiplexer";
35		mux-controls = <&mux 0>;
36		mdio-parent-bus = <&emdio1>;
37		#address-cells=<1>;
38		#size-cells = <0>;
39
40		mdio@0 { /* On-board PHY #1 RGMI1*/
41			reg = <0x00>;
42			#address-cells = <1>;
43			#size-cells = <0>;
44		};
45
46		mdio@8 { /* On-board PHY #2 RGMI2*/
47			reg = <0x8>;
48			#address-cells = <1>;
49			#size-cells = <0>;
50		};
51
52		mdio@18 { /* Slot #1 */
53			reg = <0x18>;
54			#address-cells = <1>;
55			#size-cells = <0>;
56		};
57
58		mdio@19 { /* Slot #2 */
59			reg = <0x19>;
60			#address-cells = <1>;
61			#size-cells = <0>;
62		};
63
64		mdio@1a { /* Slot #3 */
65			reg = <0x1a>;
66			#address-cells = <1>;
67			#size-cells = <0>;
68		};
69
70		mdio@1b { /* Slot #4 */
71			reg = <0x1b>;
72			#address-cells = <1>;
73			#size-cells = <0>;
74		};
75
76		mdio@1c { /* Slot #5 */
77			reg = <0x1c>;
78			#address-cells = <1>;
79			#size-cells = <0>;
80		};
81
82		mdio@1d { /* Slot #6 */
83			reg = <0x1d>;
84			#address-cells = <1>;
85			#size-cells = <0>;
86		};
87
88		mdio@1e { /* Slot #7 */
89			reg = <0x1e>;
90			#address-cells = <1>;
91			#size-cells = <0>;
92		};
93
94		mdio@1f { /* Slot #8 */
95			reg = <0x1f>;
96			#address-cells = <1>;
97			#size-cells = <0>;
98		};
99	};
100
101	mdio-mux-2 {
102		compatible = "mdio-mux-multiplexer";
103		mux-controls = <&mux 1>;
104		mdio-parent-bus = <&emdio2>;
105		#address-cells=<1>;
106		#size-cells = <0>;
107
108		mdio@0 { /* Slot #1 (secondary EMI) */
109			reg = <0x00>;
110			#address-cells = <1>;
111			#size-cells = <0>;
112		};
113
114		mdio@1 { /* Slot #2 (secondary EMI) */
115			reg = <0x01>;
116			#address-cells = <1>;
117			#size-cells = <0>;
118		};
119
120		mdio@2 { /* Slot #3 (secondary EMI) */
121			reg = <0x02>;
122			#address-cells = <1>;
123			#size-cells = <0>;
124		};
125
126		mdio@3 { /* Slot #4 (secondary EMI) */
127			reg = <0x03>;
128			#address-cells = <1>;
129			#size-cells = <0>;
130		};
131
132		mdio@4 { /* Slot #5 (secondary EMI) */
133			reg = <0x04>;
134			#address-cells = <1>;
135			#size-cells = <0>;
136		};
137
138		mdio@5 { /* Slot #6 (secondary EMI) */
139			reg = <0x05>;
140			#address-cells = <1>;
141			#size-cells = <0>;
142		};
143
144		mdio@6 { /* Slot #7 (secondary EMI) */
145			reg = <0x06>;
146			#address-cells = <1>;
147			#size-cells = <0>;
148		};
149
150		mdio@7 { /* Slot #8 (secondary EMI) */
151			reg = <0x07>;
152			#address-cells = <1>;
153			#size-cells = <0>;
154		};
155	};
156};
157
158&can0 {
159	status = "okay";
160};
161
162&can1 {
163	status = "okay";
164};
165
166&crypto {
167	status = "okay";
168};
169
170&dspi0 {
171	status = "okay";
172
173	dflash0: flash@0 {
174		#address-cells = <1>;
175		#size-cells = <1>;
176		compatible = "jedec,spi-nor";
177		reg = <0>;
178		spi-max-frequency = <1000000>;
179	};
180};
181
182&dspi1 {
183	status = "okay";
184
185	dflash1: flash@0 {
186		#address-cells = <1>;
187		#size-cells = <1>;
188		compatible = "jedec,spi-nor";
189		reg = <0>;
190		spi-max-frequency = <1000000>;
191	};
192};
193
194&dspi2 {
195	status = "okay";
196
197	dflash2: flash@0 {
198		#address-cells = <1>;
199		#size-cells = <1>;
200		compatible = "jedec,spi-nor";
201		reg = <0>;
202		spi-max-frequency = <1000000>;
203	};
204};
205
206&emdio1 {
207	status = "okay";
208};
209
210&emdio2 {
211	status = "okay";
212};
213
214&esdhc0 {
215	status = "okay";
216};
217
218&esdhc1 {
219	status = "okay";
220};
221
222&i2c0 {
223	status = "okay";
224
225	fpga@66 {
226		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
227			     "simple-mfd";
228		reg = <0x66>;
229
230		mux: mux-controller {
231			compatible = "reg-mux";
232			#mux-control-cells = <1>;
233			mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
234					<0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
235		};
236	};
237
238	i2c-mux@77 {
239		compatible = "nxp,pca9547";
240		reg = <0x77>;
241		#address-cells = <1>;
242		#size-cells = <0>;
243
244		i2c@2 {
245			#address-cells = <1>;
246			#size-cells = <0>;
247			reg = <0x2>;
248
249			power-monitor@40 {
250				compatible = "ti,ina220";
251				reg = <0x40>;
252				shunt-resistor = <500>;
253			};
254
255			power-monitor@41 {
256				compatible = "ti,ina220";
257				reg = <0x41>;
258				shunt-resistor = <1000>;
259			};
260		};
261
262		i2c@3 {
263			#address-cells = <1>;
264			#size-cells = <0>;
265			reg = <0x3>;
266
267			temperature-sensor@4c {
268				compatible = "nxp,sa56004";
269				reg = <0x4c>;
270				vcc-supply = <&sb_3v3>;
271			};
272
273			temperature-sensor@4d {
274				compatible = "nxp,sa56004";
275				reg = <0x4d>;
276				vcc-supply = <&sb_3v3>;
277			};
278
279			rtc@51 {
280				compatible = "nxp,pcf2129";
281				reg = <0x51>;
282			};
283		};
284	};
285};
286
287&sata0 {
288	status = "okay";
289};
290
291&sata1 {
292	status = "okay";
293};
294
295&sata2 {
296	status = "okay";
297};
298
299&sata3 {
300	status = "okay";
301};
302
303&uart0 {
304	status = "okay";
305};
306
307&uart1 {
308	status = "okay";
309};
310
311&usb0 {
312	status = "okay";
313};
314
315&usb1 {
316	status = "okay";
317};
318
319&sata0 {
320	status = "okay";
321};
322
323&sata1 {
324	status = "okay";
325};
326
327&sata2 {
328	status = "okay";
329};
330
331&sata3 {
332	status = "okay";
333};
334