1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 }; 36 }; 37 38 pmu { 39 compatible = "arm,cortex-a5-pmu"; 40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 41 }; 42 43 etb@740000 { 44 compatible = "arm,coresight-etb10", "arm,primecell"; 45 reg = <0x740000 0x1000>; 46 47 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 48 clock-names = "apb_pclk"; 49 50 in-ports { 51 port { 52 etb_in: endpoint { 53 remote-endpoint = <&etm_out>; 54 }; 55 }; 56 }; 57 }; 58 59 etm@73c000 { 60 compatible = "arm,coresight-etm3x", "arm,primecell"; 61 reg = <0x73c000 0x1000>; 62 63 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 64 clock-names = "apb_pclk"; 65 66 out-ports { 67 port { 68 etm_out: endpoint { 69 remote-endpoint = <&etb_in>; 70 }; 71 }; 72 }; 73 }; 74 75 memory@20000000 { 76 device_type = "memory"; 77 reg = <0x20000000 0x20000000>; 78 }; 79 80 clocks { 81 slow_xtal: slow_xtal { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 main_xtal: main_xtal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <0>; 91 }; 92 }; 93 94 ns_sram: sram@200000 { 95 compatible = "mmio-sram"; 96 reg = <0x00200000 0x20000>; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges = <0 0x00200000 0x20000>; 100 }; 101 102 ahb { 103 compatible = "simple-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges; 107 108 nfc_sram: sram@100000 { 109 compatible = "mmio-sram"; 110 no-memory-wc; 111 reg = <0x00100000 0x2400>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges = <0 0x00100000 0x2400>; 115 116 }; 117 118 usb0: gadget@300000 { 119 compatible = "atmel,sama5d3-udc"; 120 reg = <0x00300000 0x100000 121 0xfc02c000 0x400>; 122 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 123 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 124 clock-names = "pclk", "hclk"; 125 status = "disabled"; 126 }; 127 128 usb1: ohci@400000 { 129 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 130 reg = <0x00400000 0x100000>; 131 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 132 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 133 clock-names = "ohci_clk", "hclk", "uhpck"; 134 status = "disabled"; 135 }; 136 137 usb2: ehci@500000 { 138 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 139 reg = <0x00500000 0x100000>; 140 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 141 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 142 clock-names = "usb_clk", "ehci_clk"; 143 status = "disabled"; 144 }; 145 146 L2: cache-controller@a00000 { 147 compatible = "arm,pl310-cache"; 148 reg = <0x00a00000 0x1000>; 149 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 150 cache-unified; 151 cache-level = <2>; 152 }; 153 154 ebi: ebi@10000000 { 155 compatible = "atmel,sama5d3-ebi"; 156 #address-cells = <2>; 157 #size-cells = <1>; 158 atmel,smc = <&hsmc>; 159 reg = <0x10000000 0x10000000 160 0x60000000 0x30000000>; 161 ranges = <0x0 0x0 0x10000000 0x10000000 162 0x1 0x0 0x60000000 0x10000000 163 0x2 0x0 0x70000000 0x10000000 164 0x3 0x0 0x80000000 0x10000000>; 165 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 166 status = "disabled"; 167 168 nand_controller: nand-controller { 169 compatible = "atmel,sama5d3-nand-controller"; 170 atmel,nfc-sram = <&nfc_sram>; 171 atmel,nfc-io = <&nfc_io>; 172 ecc-engine = <&pmecc>; 173 #address-cells = <2>; 174 #size-cells = <1>; 175 ranges; 176 status = "disabled"; 177 }; 178 }; 179 180 sdmmc0: sdio-host@a0000000 { 181 compatible = "atmel,sama5d2-sdhci"; 182 reg = <0xa0000000 0x300>; 183 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 184 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 185 clock-names = "hclock", "multclk", "baseclk"; 186 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 187 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 188 assigned-clock-rates = <480000000>; 189 status = "disabled"; 190 }; 191 192 sdmmc1: sdio-host@b0000000 { 193 compatible = "atmel,sama5d2-sdhci"; 194 reg = <0xb0000000 0x300>; 195 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 196 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 197 clock-names = "hclock", "multclk", "baseclk"; 198 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 199 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 200 assigned-clock-rates = <480000000>; 201 status = "disabled"; 202 }; 203 204 nfc_io: nfc-io@c0000000 { 205 compatible = "atmel,sama5d3-nfc-io", "syscon"; 206 reg = <0xc0000000 0x8000000>; 207 }; 208 209 apb { 210 compatible = "simple-bus"; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges; 214 215 hlcdc: hlcdc@f0000000 { 216 compatible = "atmel,sama5d2-hlcdc"; 217 reg = <0xf0000000 0x2000>; 218 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 219 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 220 clock-names = "periph_clk","sys_clk", "slow_clk"; 221 status = "disabled"; 222 223 hlcdc-display-controller { 224 compatible = "atmel,hlcdc-display-controller"; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 228 port@0 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 reg = <0>; 232 }; 233 }; 234 235 hlcdc_pwm: hlcdc-pwm { 236 compatible = "atmel,hlcdc-pwm"; 237 #pwm-cells = <3>; 238 }; 239 }; 240 241 isc: isc@f0008000 { 242 compatible = "atmel,sama5d2-isc"; 243 reg = <0xf0008000 0x4000>; 244 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 245 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 246 clock-names = "hclock", "iscck", "gck"; 247 #clock-cells = <0>; 248 clock-output-names = "isc-mck"; 249 status = "disabled"; 250 }; 251 252 ramc0: ramc@f000c000 { 253 compatible = "atmel,sama5d3-ddramc"; 254 reg = <0xf000c000 0x200>; 255 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 256 clock-names = "ddrck", "mpddr"; 257 }; 258 259 dma0: dma-controller@f0010000 { 260 compatible = "atmel,sama5d4-dma"; 261 reg = <0xf0010000 0x1000>; 262 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 263 #dma-cells = <1>; 264 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 265 clock-names = "dma_clk"; 266 }; 267 268 /* Place dma1 here despite its address */ 269 dma1: dma-controller@f0004000 { 270 compatible = "atmel,sama5d4-dma"; 271 reg = <0xf0004000 0x1000>; 272 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 273 #dma-cells = <1>; 274 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 275 clock-names = "dma_clk"; 276 }; 277 278 pmc: pmc@f0014000 { 279 compatible = "atmel,sama5d2-pmc", "syscon"; 280 reg = <0xf0014000 0x160>; 281 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 282 #clock-cells = <2>; 283 clocks = <&clk32k>, <&main_xtal>; 284 clock-names = "slow_clk", "main_xtal"; 285 }; 286 287 qspi0: spi@f0020000 { 288 compatible = "atmel,sama5d2-qspi"; 289 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 290 reg-names = "qspi_base", "qspi_mmap"; 291 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 292 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 status = "disabled"; 296 }; 297 298 qspi1: spi@f0024000 { 299 compatible = "atmel,sama5d2-qspi"; 300 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 301 reg-names = "qspi_base", "qspi_mmap"; 302 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 303 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 status = "disabled"; 307 }; 308 309 sha@f0028000 { 310 compatible = "atmel,at91sam9g46-sha"; 311 reg = <0xf0028000 0x100>; 312 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 313 dmas = <&dma0 314 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 315 AT91_XDMAC_DT_PERID(30))>; 316 dma-names = "tx"; 317 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 318 clock-names = "sha_clk"; 319 status = "okay"; 320 }; 321 322 aes@f002c000 { 323 compatible = "atmel,at91sam9g46-aes"; 324 reg = <0xf002c000 0x100>; 325 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 326 dmas = <&dma0 327 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 328 AT91_XDMAC_DT_PERID(26))>, 329 <&dma0 330 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 331 AT91_XDMAC_DT_PERID(27))>; 332 dma-names = "tx", "rx"; 333 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 334 clock-names = "aes_clk"; 335 status = "okay"; 336 }; 337 338 spi0: spi@f8000000 { 339 compatible = "atmel,at91rm9200-spi"; 340 reg = <0xf8000000 0x100>; 341 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 342 dmas = <&dma0 343 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 344 AT91_XDMAC_DT_PERID(6))>, 345 <&dma0 346 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 347 AT91_XDMAC_DT_PERID(7))>; 348 dma-names = "tx", "rx"; 349 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 350 clock-names = "spi_clk"; 351 atmel,fifo-size = <16>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 status = "disabled"; 355 }; 356 357 ssc0: ssc@f8004000 { 358 compatible = "atmel,at91sam9g45-ssc"; 359 reg = <0xf8004000 0x4000>; 360 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 361 dmas = <&dma0 362 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 363 AT91_XDMAC_DT_PERID(21))>, 364 <&dma0 365 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 366 AT91_XDMAC_DT_PERID(22))>; 367 dma-names = "tx", "rx"; 368 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 369 clock-names = "pclk"; 370 status = "disabled"; 371 }; 372 373 macb0: ethernet@f8008000 { 374 compatible = "atmel,sama5d2-gem"; 375 reg = <0xf8008000 0x1000>; 376 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 377 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 378 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 379 #address-cells = <1>; 380 #size-cells = <0>; 381 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 382 clock-names = "hclk", "pclk"; 383 status = "disabled"; 384 }; 385 386 tcb0: timer@f800c000 { 387 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <0xf800c000 0x100>; 391 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 392 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 393 clock-names = "t0_clk", "gclk", "slow_clk"; 394 }; 395 396 tcb1: timer@f8010000 { 397 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 reg = <0xf8010000 0x100>; 401 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 402 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 403 clock-names = "t0_clk", "gclk", "slow_clk"; 404 }; 405 406 hsmc: hsmc@f8014000 { 407 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 408 reg = <0xf8014000 0x1000>; 409 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 410 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 411 #address-cells = <1>; 412 #size-cells = <1>; 413 ranges; 414 415 pmecc: ecc-engine@f8014070 { 416 compatible = "atmel,sama5d2-pmecc"; 417 reg = <0xf8014070 0x490>, 418 <0xf8014500 0x100>; 419 }; 420 }; 421 422 pdmic: pdmic@f8018000 { 423 compatible = "atmel,sama5d2-pdmic"; 424 reg = <0xf8018000 0x124>; 425 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 426 dmas = <&dma0 427 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 428 | AT91_XDMAC_DT_PERID(50))>; 429 dma-names = "rx"; 430 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 431 clock-names = "pclk", "gclk"; 432 status = "disabled"; 433 }; 434 435 uart0: serial@f801c000 { 436 compatible = "atmel,at91sam9260-usart"; 437 reg = <0xf801c000 0x100>; 438 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 439 dmas = <&dma0 440 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 441 AT91_XDMAC_DT_PERID(35))>, 442 <&dma0 443 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 444 AT91_XDMAC_DT_PERID(36))>; 445 dma-names = "tx", "rx"; 446 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 447 clock-names = "usart"; 448 status = "disabled"; 449 }; 450 451 uart1: serial@f8020000 { 452 compatible = "atmel,at91sam9260-usart"; 453 reg = <0xf8020000 0x100>; 454 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 455 dmas = <&dma0 456 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 457 AT91_XDMAC_DT_PERID(37))>, 458 <&dma0 459 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 460 AT91_XDMAC_DT_PERID(38))>; 461 dma-names = "tx", "rx"; 462 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 463 clock-names = "usart"; 464 status = "disabled"; 465 }; 466 467 uart2: serial@f8024000 { 468 compatible = "atmel,at91sam9260-usart"; 469 reg = <0xf8024000 0x100>; 470 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 471 dmas = <&dma0 472 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 473 AT91_XDMAC_DT_PERID(39))>, 474 <&dma0 475 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 476 AT91_XDMAC_DT_PERID(40))>; 477 dma-names = "tx", "rx"; 478 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 479 clock-names = "usart"; 480 status = "disabled"; 481 }; 482 483 i2c0: i2c@f8028000 { 484 compatible = "atmel,sama5d2-i2c"; 485 reg = <0xf8028000 0x100>; 486 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 487 dmas = <&dma0 488 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 489 AT91_XDMAC_DT_PERID(0))>, 490 <&dma0 491 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 492 AT91_XDMAC_DT_PERID(1))>; 493 dma-names = "tx", "rx"; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 497 atmel,fifo-size = <16>; 498 status = "disabled"; 499 }; 500 501 pwm0: pwm@f802c000 { 502 compatible = "atmel,sama5d2-pwm"; 503 reg = <0xf802c000 0x4000>; 504 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 505 #pwm-cells = <3>; 506 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 507 status = "disabled"; 508 }; 509 510 sfr: sfr@f8030000 { 511 compatible = "atmel,sama5d2-sfr", "syscon"; 512 reg = <0xf8030000 0x98>; 513 }; 514 515 flx0: flexcom@f8034000 { 516 compatible = "atmel,sama5d2-flexcom"; 517 reg = <0xf8034000 0x200>; 518 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 519 #address-cells = <1>; 520 #size-cells = <1>; 521 ranges = <0x0 0xf8034000 0x800>; 522 status = "disabled"; 523 524 uart5: serial@200 { 525 compatible = "atmel,at91sam9260-usart"; 526 reg = <0x200 0x200>; 527 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 528 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 529 clock-names = "usart"; 530 dmas = <&dma0 531 (AT91_XDMAC_DT_MEM_IF(0) | 532 AT91_XDMAC_DT_PER_IF(1) | 533 AT91_XDMAC_DT_PERID(11))>, 534 <&dma0 535 (AT91_XDMAC_DT_MEM_IF(0) | 536 AT91_XDMAC_DT_PER_IF(1) | 537 AT91_XDMAC_DT_PERID(12))>; 538 dma-names = "tx", "rx"; 539 atmel,fifo-size = <32>; 540 status = "disabled"; 541 }; 542 543 spi2: spi@400 { 544 compatible = "atmel,at91rm9200-spi"; 545 reg = <0x400 0x200>; 546 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 550 clock-names = "spi_clk"; 551 dmas = <&dma0 552 (AT91_XDMAC_DT_MEM_IF(0) | 553 AT91_XDMAC_DT_PER_IF(1) | 554 AT91_XDMAC_DT_PERID(11))>, 555 <&dma0 556 (AT91_XDMAC_DT_MEM_IF(0) | 557 AT91_XDMAC_DT_PER_IF(1) | 558 AT91_XDMAC_DT_PERID(12))>; 559 dma-names = "tx", "rx"; 560 atmel,fifo-size = <16>; 561 status = "disabled"; 562 }; 563 564 i2c2: i2c@600 { 565 compatible = "atmel,sama5d2-i2c"; 566 reg = <0x600 0x200>; 567 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 571 dmas = <&dma0 572 (AT91_XDMAC_DT_MEM_IF(0) | 573 AT91_XDMAC_DT_PER_IF(1) | 574 AT91_XDMAC_DT_PERID(11))>, 575 <&dma0 576 (AT91_XDMAC_DT_MEM_IF(0) | 577 AT91_XDMAC_DT_PER_IF(1) | 578 AT91_XDMAC_DT_PERID(12))>; 579 dma-names = "tx", "rx"; 580 atmel,fifo-size = <16>; 581 status = "disabled"; 582 }; 583 }; 584 585 flx1: flexcom@f8038000 { 586 compatible = "atmel,sama5d2-flexcom"; 587 reg = <0xf8038000 0x200>; 588 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 589 #address-cells = <1>; 590 #size-cells = <1>; 591 ranges = <0x0 0xf8038000 0x800>; 592 status = "disabled"; 593 594 uart6: serial@200 { 595 compatible = "atmel,at91sam9260-usart"; 596 reg = <0x200 0x200>; 597 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 598 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 599 clock-names = "usart"; 600 dmas = <&dma0 601 (AT91_XDMAC_DT_MEM_IF(0) | 602 AT91_XDMAC_DT_PER_IF(1) | 603 AT91_XDMAC_DT_PERID(13))>, 604 <&dma0 605 (AT91_XDMAC_DT_MEM_IF(0) | 606 AT91_XDMAC_DT_PER_IF(1) | 607 AT91_XDMAC_DT_PERID(14))>; 608 dma-names = "tx", "rx"; 609 atmel,fifo-size = <32>; 610 status = "disabled"; 611 }; 612 613 spi3: spi@400 { 614 compatible = "atmel,at91rm9200-spi"; 615 reg = <0x400 0x200>; 616 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 620 clock-names = "spi_clk"; 621 dmas = <&dma0 622 (AT91_XDMAC_DT_MEM_IF(0) | 623 AT91_XDMAC_DT_PER_IF(1) | 624 AT91_XDMAC_DT_PERID(13))>, 625 <&dma0 626 (AT91_XDMAC_DT_MEM_IF(0) | 627 AT91_XDMAC_DT_PER_IF(1) | 628 AT91_XDMAC_DT_PERID(14))>; 629 dma-names = "tx", "rx"; 630 atmel,fifo-size = <16>; 631 status = "disabled"; 632 }; 633 634 i2c3: i2c@600 { 635 compatible = "atmel,sama5d2-i2c"; 636 reg = <0x600 0x200>; 637 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 641 dmas = <&dma0 642 (AT91_XDMAC_DT_MEM_IF(0) | 643 AT91_XDMAC_DT_PER_IF(1) | 644 AT91_XDMAC_DT_PERID(13))>, 645 <&dma0 646 (AT91_XDMAC_DT_MEM_IF(0) | 647 AT91_XDMAC_DT_PER_IF(1) | 648 AT91_XDMAC_DT_PERID(14))>; 649 dma-names = "tx", "rx"; 650 atmel,fifo-size = <16>; 651 status = "disabled"; 652 }; 653 }; 654 655 securam: sram@f8044000 { 656 compatible = "atmel,sama5d2-securam", "mmio-sram"; 657 reg = <0xf8044000 0x1420>; 658 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 659 #address-cells = <1>; 660 #size-cells = <1>; 661 no-memory-wc; 662 ranges = <0 0xf8044000 0x1420>; 663 }; 664 665 reset_controller: rstc@f8048000 { 666 compatible = "atmel,sama5d3-rstc"; 667 reg = <0xf8048000 0x10>; 668 clocks = <&clk32k>; 669 }; 670 671 shutdown_controller: shdwc@f8048010 { 672 compatible = "atmel,sama5d2-shdwc"; 673 reg = <0xf8048010 0x10>; 674 clocks = <&clk32k>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 atmel,wakeup-rtc-timer; 678 }; 679 680 pit: timer@f8048030 { 681 compatible = "atmel,at91sam9260-pit"; 682 reg = <0xf8048030 0x10>; 683 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 684 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 685 }; 686 687 watchdog: watchdog@f8048040 { 688 compatible = "atmel,sama5d4-wdt"; 689 reg = <0xf8048040 0x10>; 690 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 691 clocks = <&clk32k>; 692 status = "disabled"; 693 }; 694 695 clk32k: sckc@f8048050 { 696 compatible = "atmel,sama5d4-sckc"; 697 reg = <0xf8048050 0x4>; 698 699 clocks = <&slow_xtal>; 700 #clock-cells = <0>; 701 }; 702 703 rtc: rtc@f80480b0 { 704 compatible = "atmel,sama5d2-rtc"; 705 reg = <0xf80480b0 0x30>; 706 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 707 clocks = <&clk32k>; 708 }; 709 710 i2s0: i2s@f8050000 { 711 compatible = "atmel,sama5d2-i2s"; 712 reg = <0xf8050000 0x100>; 713 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 714 dmas = <&dma0 715 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 716 AT91_XDMAC_DT_PERID(31))>, 717 <&dma0 718 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 719 AT91_XDMAC_DT_PERID(32))>; 720 dma-names = "tx", "rx"; 721 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 722 clock-names = "pclk", "gclk"; 723 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 724 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 725 status = "disabled"; 726 }; 727 728 can0: can@f8054000 { 729 compatible = "bosch,m_can"; 730 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 731 reg-names = "m_can", "message_ram"; 732 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 733 <64 IRQ_TYPE_LEVEL_HIGH 7>; 734 interrupt-names = "int0", "int1"; 735 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 736 clock-names = "hclk", "cclk"; 737 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 738 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 739 assigned-clock-rates = <40000000>; 740 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 741 status = "disabled"; 742 }; 743 744 spi1: spi@fc000000 { 745 compatible = "atmel,at91rm9200-spi"; 746 reg = <0xfc000000 0x100>; 747 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 748 dmas = <&dma0 749 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 750 AT91_XDMAC_DT_PERID(8))>, 751 <&dma0 752 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 753 AT91_XDMAC_DT_PERID(9))>; 754 dma-names = "tx", "rx"; 755 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 756 clock-names = "spi_clk"; 757 atmel,fifo-size = <16>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 uart3: serial@fc008000 { 764 compatible = "atmel,at91sam9260-usart"; 765 reg = <0xfc008000 0x100>; 766 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 767 dmas = <&dma1 768 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 769 AT91_XDMAC_DT_PERID(41))>, 770 <&dma1 771 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 772 AT91_XDMAC_DT_PERID(42))>; 773 dma-names = "tx", "rx"; 774 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 775 clock-names = "usart"; 776 status = "disabled"; 777 }; 778 779 uart4: serial@fc00c000 { 780 compatible = "atmel,at91sam9260-usart"; 781 reg = <0xfc00c000 0x100>; 782 dmas = <&dma0 783 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 784 AT91_XDMAC_DT_PERID(43))>, 785 <&dma0 786 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 787 AT91_XDMAC_DT_PERID(44))>; 788 dma-names = "tx", "rx"; 789 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 790 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 791 clock-names = "usart"; 792 status = "disabled"; 793 }; 794 795 flx2: flexcom@fc010000 { 796 compatible = "atmel,sama5d2-flexcom"; 797 reg = <0xfc010000 0x200>; 798 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 799 #address-cells = <1>; 800 #size-cells = <1>; 801 ranges = <0x0 0xfc010000 0x800>; 802 status = "disabled"; 803 804 uart7: serial@200 { 805 compatible = "atmel,at91sam9260-usart"; 806 reg = <0x200 0x200>; 807 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 808 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 809 clock-names = "usart"; 810 dmas = <&dma0 811 (AT91_XDMAC_DT_MEM_IF(0) | 812 AT91_XDMAC_DT_PER_IF(1) | 813 AT91_XDMAC_DT_PERID(15))>, 814 <&dma0 815 (AT91_XDMAC_DT_MEM_IF(0) | 816 AT91_XDMAC_DT_PER_IF(1) | 817 AT91_XDMAC_DT_PERID(16))>; 818 dma-names = "tx", "rx"; 819 atmel,fifo-size = <32>; 820 status = "disabled"; 821 }; 822 823 spi4: spi@400 { 824 compatible = "atmel,at91rm9200-spi"; 825 reg = <0x400 0x200>; 826 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 830 clock-names = "spi_clk"; 831 dmas = <&dma0 832 (AT91_XDMAC_DT_MEM_IF(0) | 833 AT91_XDMAC_DT_PER_IF(1) | 834 AT91_XDMAC_DT_PERID(15))>, 835 <&dma0 836 (AT91_XDMAC_DT_MEM_IF(0) | 837 AT91_XDMAC_DT_PER_IF(1) | 838 AT91_XDMAC_DT_PERID(16))>; 839 dma-names = "tx", "rx"; 840 atmel,fifo-size = <16>; 841 status = "disabled"; 842 }; 843 844 i2c4: i2c@600 { 845 compatible = "atmel,sama5d2-i2c"; 846 reg = <0x600 0x200>; 847 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 851 dmas = <&dma0 852 (AT91_XDMAC_DT_MEM_IF(0) | 853 AT91_XDMAC_DT_PER_IF(1) | 854 AT91_XDMAC_DT_PERID(15))>, 855 <&dma0 856 (AT91_XDMAC_DT_MEM_IF(0) | 857 AT91_XDMAC_DT_PER_IF(1) | 858 AT91_XDMAC_DT_PERID(16))>; 859 dma-names = "tx", "rx"; 860 atmel,fifo-size = <16>; 861 status = "disabled"; 862 }; 863 }; 864 865 flx3: flexcom@fc014000 { 866 compatible = "atmel,sama5d2-flexcom"; 867 reg = <0xfc014000 0x200>; 868 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 869 #address-cells = <1>; 870 #size-cells = <1>; 871 ranges = <0x0 0xfc014000 0x800>; 872 status = "disabled"; 873 874 uart8: serial@200 { 875 compatible = "atmel,at91sam9260-usart"; 876 reg = <0x200 0x200>; 877 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 878 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 879 clock-names = "usart"; 880 dmas = <&dma0 881 (AT91_XDMAC_DT_MEM_IF(0) | 882 AT91_XDMAC_DT_PER_IF(1) | 883 AT91_XDMAC_DT_PERID(17))>, 884 <&dma0 885 (AT91_XDMAC_DT_MEM_IF(0) | 886 AT91_XDMAC_DT_PER_IF(1) | 887 AT91_XDMAC_DT_PERID(18))>; 888 dma-names = "tx", "rx"; 889 atmel,fifo-size = <32>; 890 status = "disabled"; 891 }; 892 893 spi5: spi@400 { 894 compatible = "atmel,at91rm9200-spi"; 895 reg = <0x400 0x200>; 896 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 900 clock-names = "spi_clk"; 901 dmas = <&dma0 902 (AT91_XDMAC_DT_MEM_IF(0) | 903 AT91_XDMAC_DT_PER_IF(1) | 904 AT91_XDMAC_DT_PERID(17))>, 905 <&dma0 906 (AT91_XDMAC_DT_MEM_IF(0) | 907 AT91_XDMAC_DT_PER_IF(1) | 908 AT91_XDMAC_DT_PERID(18))>; 909 dma-names = "tx", "rx"; 910 atmel,fifo-size = <16>; 911 status = "disabled"; 912 }; 913 914 i2c5: i2c@600 { 915 compatible = "atmel,sama5d2-i2c"; 916 reg = <0x600 0x200>; 917 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 921 dmas = <&dma0 922 (AT91_XDMAC_DT_MEM_IF(0) | 923 AT91_XDMAC_DT_PER_IF(1) | 924 AT91_XDMAC_DT_PERID(17))>, 925 <&dma0 926 (AT91_XDMAC_DT_MEM_IF(0) | 927 AT91_XDMAC_DT_PER_IF(1) | 928 AT91_XDMAC_DT_PERID(18))>; 929 dma-names = "tx", "rx"; 930 atmel,fifo-size = <16>; 931 status = "disabled"; 932 }; 933 934 }; 935 936 flx4: flexcom@fc018000 { 937 compatible = "atmel,sama5d2-flexcom"; 938 reg = <0xfc018000 0x200>; 939 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 ranges = <0x0 0xfc018000 0x800>; 943 status = "disabled"; 944 945 uart9: serial@200 { 946 compatible = "atmel,at91sam9260-usart"; 947 reg = <0x200 0x200>; 948 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 949 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 950 clock-names = "usart"; 951 dmas = <&dma0 952 (AT91_XDMAC_DT_MEM_IF(0) | 953 AT91_XDMAC_DT_PER_IF(1) | 954 AT91_XDMAC_DT_PERID(19))>, 955 <&dma0 956 (AT91_XDMAC_DT_MEM_IF(0) | 957 AT91_XDMAC_DT_PER_IF(1) | 958 AT91_XDMAC_DT_PERID(20))>; 959 dma-names = "tx", "rx"; 960 atmel,fifo-size = <32>; 961 status = "disabled"; 962 }; 963 964 spi6: spi@400 { 965 compatible = "atmel,at91rm9200-spi"; 966 reg = <0x400 0x200>; 967 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 971 clock-names = "spi_clk"; 972 dmas = <&dma0 973 (AT91_XDMAC_DT_MEM_IF(0) | 974 AT91_XDMAC_DT_PER_IF(1) | 975 AT91_XDMAC_DT_PERID(19))>, 976 <&dma0 977 (AT91_XDMAC_DT_MEM_IF(0) | 978 AT91_XDMAC_DT_PER_IF(1) | 979 AT91_XDMAC_DT_PERID(20))>; 980 dma-names = "tx", "rx"; 981 atmel,fifo-size = <16>; 982 status = "disabled"; 983 }; 984 985 i2c6: i2c@600 { 986 compatible = "atmel,sama5d2-i2c"; 987 reg = <0x600 0x200>; 988 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 992 dmas = <&dma0 993 (AT91_XDMAC_DT_MEM_IF(0) | 994 AT91_XDMAC_DT_PER_IF(1) | 995 AT91_XDMAC_DT_PERID(19))>, 996 <&dma0 997 (AT91_XDMAC_DT_MEM_IF(0) | 998 AT91_XDMAC_DT_PER_IF(1) | 999 AT91_XDMAC_DT_PERID(20))>; 1000 dma-names = "tx", "rx"; 1001 atmel,fifo-size = <16>; 1002 status = "disabled"; 1003 }; 1004 }; 1005 1006 trng@fc01c000 { 1007 compatible = "atmel,at91sam9g45-trng"; 1008 reg = <0xfc01c000 0x100>; 1009 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1010 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1011 status = "disabled"; 1012 secure-status = "okay"; 1013 }; 1014 1015 aic: interrupt-controller@fc020000 { 1016 #interrupt-cells = <3>; 1017 compatible = "atmel,sama5d2-aic"; 1018 interrupt-controller; 1019 reg = <0xfc020000 0x200>; 1020 atmel,external-irqs = <49>; 1021 }; 1022 1023 i2c1: i2c@fc028000 { 1024 compatible = "atmel,sama5d2-i2c"; 1025 reg = <0xfc028000 0x100>; 1026 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1027 dmas = <&dma0 1028 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1029 AT91_XDMAC_DT_PERID(2))>, 1030 <&dma0 1031 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1032 AT91_XDMAC_DT_PERID(3))>; 1033 dma-names = "tx", "rx"; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1037 atmel,fifo-size = <16>; 1038 status = "disabled"; 1039 }; 1040 1041 adc: adc@fc030000 { 1042 compatible = "atmel,sama5d2-adc"; 1043 reg = <0xfc030000 0x100>; 1044 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1045 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1046 clock-names = "adc_clk"; 1047 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1048 dma-names = "rx"; 1049 atmel,min-sample-rate-hz = <200000>; 1050 atmel,max-sample-rate-hz = <20000000>; 1051 atmel,startup-time-ms = <4>; 1052 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1053 #io-channel-cells = <1>; 1054 status = "disabled"; 1055 }; 1056 1057 resistive_touch: resistive-touch { 1058 compatible = "resistive-adc-touch"; 1059 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1060 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1061 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1062 io-channel-names = "x", "y", "pressure"; 1063 touchscreen-min-pressure = <50000>; 1064 status = "disabled"; 1065 }; 1066 1067 pioA: pinctrl@fc038000 { 1068 compatible = "atmel,sama5d2-pinctrl"; 1069 reg = <0xfc038000 0x600>; 1070 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1071 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1072 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1073 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1074 interrupt-controller; 1075 #interrupt-cells = <2>; 1076 gpio-controller; 1077 #gpio-cells = <2>; 1078 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1079 }; 1080 1081 pioBU: secumod@fc040000 { 1082 compatible = "atmel,sama5d2-secumod", "syscon"; 1083 reg = <0xfc040000 0x100>; 1084 1085 gpio-controller; 1086 #gpio-cells = <2>; 1087 }; 1088 1089 tdes@fc044000 { 1090 compatible = "atmel,at91sam9g46-tdes"; 1091 reg = <0xfc044000 0x100>; 1092 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1093 dmas = <&dma0 1094 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1095 AT91_XDMAC_DT_PERID(28))>, 1096 <&dma0 1097 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1098 AT91_XDMAC_DT_PERID(29))>; 1099 dma-names = "tx", "rx"; 1100 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1101 clock-names = "tdes_clk"; 1102 status = "okay"; 1103 }; 1104 1105 classd: classd@fc048000 { 1106 compatible = "atmel,sama5d2-classd"; 1107 reg = <0xfc048000 0x100>; 1108 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1109 dmas = <&dma0 1110 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1111 AT91_XDMAC_DT_PERID(47))>; 1112 dma-names = "tx"; 1113 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1114 clock-names = "pclk", "gclk"; 1115 status = "disabled"; 1116 }; 1117 1118 i2s1: i2s@fc04c000 { 1119 compatible = "atmel,sama5d2-i2s"; 1120 reg = <0xfc04c000 0x100>; 1121 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1122 dmas = <&dma0 1123 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1124 AT91_XDMAC_DT_PERID(33))>, 1125 <&dma0 1126 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1127 AT91_XDMAC_DT_PERID(34))>; 1128 dma-names = "tx", "rx"; 1129 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1130 clock-names = "pclk", "gclk"; 1131 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1132 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1133 status = "disabled"; 1134 }; 1135 1136 can1: can@fc050000 { 1137 compatible = "bosch,m_can"; 1138 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1139 reg-names = "m_can", "message_ram"; 1140 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1141 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1142 interrupt-names = "int0", "int1"; 1143 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1144 clock-names = "hclk", "cclk"; 1145 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1146 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1147 assigned-clock-rates = <40000000>; 1148 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1149 status = "disabled"; 1150 }; 1151 1152 sfrbu: sfr@fc05c000 { 1153 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1154 reg = <0xfc05c000 0x20>; 1155 }; 1156 1157 chipid@fc069000 { 1158 compatible = "atmel,sama5d2-chipid"; 1159 reg = <0xfc069000 0x8>; 1160 }; 1161 }; 1162 }; 1163}; 1164