1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/pinctrl/stm32-pinfunc.h> 7 8&pinctrl { 9 adc1_in6_pins_a: adc1-in6 { 10 pins { 11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>; 12 }; 13 }; 14 15 adc12_ain_pins_a: adc12-ain-0 { 16 pins { 17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ 18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */ 20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */ 21 }; 22 }; 23 24 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { 25 pins { 26 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ 27 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ 28 }; 29 }; 30 31 cec_pins_a: cec-0 { 32 pins { 33 pinmux = <STM32_PINMUX('A', 15, AF4)>; 34 bias-disable; 35 drive-open-drain; 36 slew-rate = <0>; 37 }; 38 }; 39 40 cec_pins_sleep_a: cec-sleep-0 { 41 pins { 42 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ 43 }; 44 }; 45 46 cec_pins_b: cec-1 { 47 pins { 48 pinmux = <STM32_PINMUX('B', 6, AF5)>; 49 bias-disable; 50 drive-open-drain; 51 slew-rate = <0>; 52 }; 53 }; 54 55 cec_pins_sleep_b: cec-sleep-1 { 56 pins { 57 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ 58 }; 59 }; 60 61 dac_ch1_pins_a: dac-ch1 { 62 pins { 63 pinmux = <STM32_PINMUX('A', 4, ANALOG)>; 64 }; 65 }; 66 67 dac_ch2_pins_a: dac-ch2 { 68 pins { 69 pinmux = <STM32_PINMUX('A', 5, ANALOG)>; 70 }; 71 }; 72 73 dcmi_pins_a: dcmi-0 { 74 pins { 75 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ 76 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 77 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 78 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ 79 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 80 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 81 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ 82 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ 83 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ 84 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ 85 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ 86 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ 87 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ 88 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ 89 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ 90 bias-disable; 91 }; 92 }; 93 94 dcmi_sleep_pins_a: dcmi-sleep-0 { 95 pins { 96 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ 97 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 98 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 99 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ 100 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 101 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 102 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ 103 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ 104 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ 105 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ 106 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ 107 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ 108 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ 109 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ 110 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ 111 }; 112 }; 113 114 ethernet0_rgmii_pins_a: rgmii-0 { 115 pins1 { 116 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 117 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 118 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 119 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 120 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 121 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 122 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 123 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 124 bias-disable; 125 drive-push-pull; 126 slew-rate = <2>; 127 }; 128 pins2 { 129 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 130 bias-disable; 131 drive-push-pull; 132 slew-rate = <0>; 133 }; 134 pins3 { 135 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 136 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 137 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ 138 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 139 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 140 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 141 bias-disable; 142 }; 143 }; 144 145 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { 146 pins1 { 147 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 148 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 149 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 150 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 151 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 152 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 153 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 154 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 155 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 156 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 157 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 158 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ 159 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 160 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 161 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 162 }; 163 }; 164 165 fmc_pins_a: fmc-0 { 166 pins1 { 167 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 168 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 169 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ 170 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ 171 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 172 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 173 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 174 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 175 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 176 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 177 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 178 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 179 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ 180 bias-disable; 181 drive-push-pull; 182 slew-rate = <1>; 183 }; 184 pins2 { 185 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ 186 bias-pull-up; 187 }; 188 }; 189 190 fmc_sleep_pins_a: fmc-sleep-0 { 191 pins { 192 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 193 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 194 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ 195 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ 196 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 197 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 198 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 199 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 200 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 201 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 202 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 203 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 204 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ 205 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ 206 }; 207 }; 208 209 i2c1_pins_a: i2c1-0 { 210 pins { 211 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ 212 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 213 bias-disable; 214 drive-open-drain; 215 slew-rate = <0>; 216 }; 217 }; 218 219 i2c1_pins_sleep_a: i2c1-1 { 220 pins { 221 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ 222 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 223 }; 224 }; 225 226 i2c1_pins_b: i2c1-2 { 227 pins { 228 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ 229 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 230 bias-disable; 231 drive-open-drain; 232 slew-rate = <0>; 233 }; 234 }; 235 236 i2c1_pins_sleep_b: i2c1-3 { 237 pins { 238 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ 239 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 240 }; 241 }; 242 243 i2c2_pins_a: i2c2-0 { 244 pins { 245 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ 246 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 247 bias-disable; 248 drive-open-drain; 249 slew-rate = <0>; 250 }; 251 }; 252 253 i2c2_pins_sleep_a: i2c2-1 { 254 pins { 255 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ 256 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 257 }; 258 }; 259 260 i2c2_pins_b1: i2c2-2 { 261 pins { 262 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 263 bias-disable; 264 drive-open-drain; 265 slew-rate = <0>; 266 }; 267 }; 268 269 i2c2_pins_sleep_b1: i2c2-3 { 270 pins { 271 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 272 }; 273 }; 274 275 i2c5_pins_a: i2c5-0 { 276 pins { 277 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ 278 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ 279 bias-disable; 280 drive-open-drain; 281 slew-rate = <0>; 282 }; 283 }; 284 285 i2c5_pins_sleep_a: i2c5-1 { 286 pins { 287 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ 288 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ 289 290 }; 291 }; 292 293 i2s2_pins_a: i2s2-0 { 294 pins { 295 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ 296 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ 297 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ 298 slew-rate = <1>; 299 drive-push-pull; 300 bias-disable; 301 }; 302 }; 303 304 i2s2_pins_sleep_a: i2s2-1 { 305 pins { 306 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ 307 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ 308 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ 309 }; 310 }; 311 312 ltdc_pins_a: ltdc-a-0 { 313 pins { 314 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ 315 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 316 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 317 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ 318 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ 319 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 320 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 321 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 322 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ 323 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ 324 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 325 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 326 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 327 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ 328 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 329 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ 330 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 331 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ 332 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ 333 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ 334 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 335 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 336 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 337 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 338 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ 339 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 340 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 341 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ 342 bias-disable; 343 drive-push-pull; 344 slew-rate = <1>; 345 }; 346 }; 347 348 ltdc_pins_sleep_a: ltdc-a-1 { 349 pins { 350 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 351 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 352 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 353 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ 354 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ 355 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 356 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 357 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 358 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ 359 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ 360 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 361 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 362 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 363 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ 364 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 365 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ 366 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 367 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ 368 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ 369 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ 370 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 371 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 372 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 373 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 374 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ 375 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 376 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 377 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ 378 }; 379 }; 380 381 ltdc_pins_b: ltdc-b-0 { 382 pins { 383 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ 384 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ 385 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ 386 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ 387 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ 388 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ 389 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ 390 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ 391 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ 392 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ 393 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ 394 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ 395 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ 396 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ 397 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ 398 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ 399 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ 400 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ 401 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ 402 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ 403 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ 404 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ 405 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ 406 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ 407 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ 408 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ 409 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ 410 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ 411 bias-disable; 412 drive-push-pull; 413 slew-rate = <1>; 414 }; 415 }; 416 417 ltdc_pins_sleep_b: ltdc-b-1 { 418 pins { 419 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ 420 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ 421 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ 422 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ 423 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ 424 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ 425 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ 426 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ 427 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ 428 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ 429 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ 430 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ 431 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ 432 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ 433 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ 434 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ 435 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ 436 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ 437 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ 438 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ 439 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ 440 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ 441 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ 442 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ 443 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ 444 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ 445 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ 446 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ 447 }; 448 }; 449 450 m_can1_pins_a: m-can1-0 { 451 pins1 { 452 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 453 slew-rate = <1>; 454 drive-push-pull; 455 bias-disable; 456 }; 457 pins2 { 458 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ 459 bias-disable; 460 }; 461 }; 462 463 m_can1_sleep_pins_a: m_can1-sleep-0 { 464 pins { 465 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ 466 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ 467 }; 468 }; 469 470 pwm1_pins_a: pwm1-0 { 471 pins { 472 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ 473 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ 474 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */ 475 bias-pull-down; 476 drive-push-pull; 477 slew-rate = <0>; 478 }; 479 }; 480 481 pwm1_sleep_pins_a: pwm1-sleep-0 { 482 pins { 483 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ 484 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ 485 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */ 486 }; 487 }; 488 489 pwm2_pins_a: pwm2-0 { 490 pins { 491 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ 492 bias-pull-down; 493 drive-push-pull; 494 slew-rate = <0>; 495 }; 496 }; 497 498 pwm2_sleep_pins_a: pwm2-sleep-0 { 499 pins { 500 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ 501 }; 502 }; 503 504 pwm3_pins_a: pwm3-0 { 505 pins { 506 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ 507 bias-pull-down; 508 drive-push-pull; 509 slew-rate = <0>; 510 }; 511 }; 512 513 pwm3_sleep_pins_a: pwm3-sleep-0 { 514 pins { 515 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ 516 }; 517 }; 518 519 pwm4_pins_a: pwm4-0 { 520 pins { 521 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ 522 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ 523 bias-pull-down; 524 drive-push-pull; 525 slew-rate = <0>; 526 }; 527 }; 528 529 pwm4_sleep_pins_a: pwm4-sleep-0 { 530 pins { 531 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ 532 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ 533 }; 534 }; 535 536 pwm4_pins_b: pwm4-1 { 537 pins { 538 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ 539 bias-pull-down; 540 drive-push-pull; 541 slew-rate = <0>; 542 }; 543 }; 544 545 pwm4_sleep_pins_b: pwm4-sleep-1 { 546 pins { 547 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ 548 }; 549 }; 550 551 pwm5_pins_a: pwm5-0 { 552 pins { 553 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ 554 bias-pull-down; 555 drive-push-pull; 556 slew-rate = <0>; 557 }; 558 }; 559 560 pwm5_sleep_pins_a: pwm5-sleep-0 { 561 pins { 562 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ 563 }; 564 }; 565 566 pwm8_pins_a: pwm8-0 { 567 pins { 568 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ 569 bias-pull-down; 570 drive-push-pull; 571 slew-rate = <0>; 572 }; 573 }; 574 575 pwm8_sleep_pins_a: pwm8-sleep-0 { 576 pins { 577 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ 578 }; 579 }; 580 581 pwm12_pins_a: pwm12-0 { 582 pins { 583 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ 584 bias-pull-down; 585 drive-push-pull; 586 slew-rate = <0>; 587 }; 588 }; 589 590 pwm12_sleep_pins_a: pwm12-sleep-0 { 591 pins { 592 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ 593 }; 594 }; 595 596 qspi_clk_pins_a: qspi-clk-0 { 597 pins { 598 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ 599 bias-disable; 600 drive-push-pull; 601 slew-rate = <3>; 602 }; 603 }; 604 605 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { 606 pins { 607 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ 608 }; 609 }; 610 611 qspi_bk1_pins_a: qspi-bk1-0 { 612 pins1 { 613 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 614 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 615 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ 616 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ 617 bias-disable; 618 drive-push-pull; 619 slew-rate = <1>; 620 }; 621 pins2 { 622 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ 623 bias-pull-up; 624 drive-push-pull; 625 slew-rate = <1>; 626 }; 627 }; 628 629 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { 630 pins { 631 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ 632 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ 633 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ 634 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ 635 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ 636 }; 637 }; 638 639 qspi_bk2_pins_a: qspi-bk2-0 { 640 pins1 { 641 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ 642 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ 643 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ 644 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ 645 bias-disable; 646 drive-push-pull; 647 slew-rate = <1>; 648 }; 649 pins2 { 650 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ 651 bias-pull-up; 652 drive-push-pull; 653 slew-rate = <1>; 654 }; 655 }; 656 657 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { 658 pins { 659 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ 660 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ 661 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ 662 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ 663 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ 664 }; 665 }; 666 667 sai2a_pins_a: sai2a-0 { 668 pins { 669 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ 670 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 671 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 672 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ 673 slew-rate = <0>; 674 drive-push-pull; 675 bias-disable; 676 }; 677 }; 678 679 sai2a_sleep_pins_a: sai2a-1 { 680 pins { 681 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ 682 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 683 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 684 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ 685 }; 686 }; 687 688 sai2b_pins_a: sai2b-0 { 689 pins1 { 690 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ 691 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ 692 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ 693 slew-rate = <0>; 694 drive-push-pull; 695 bias-disable; 696 }; 697 pins2 { 698 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 699 bias-disable; 700 }; 701 }; 702 703 sai2b_sleep_pins_a: sai2b-1 { 704 pins { 705 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ 706 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ 707 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ 708 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ 709 }; 710 }; 711 712 sai2b_pins_b: sai2b-2 { 713 pins { 714 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 715 bias-disable; 716 }; 717 }; 718 719 sai2b_sleep_pins_b: sai2b-3 { 720 pins { 721 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 722 }; 723 }; 724 725 sai4a_pins_a: sai4a-0 { 726 pins { 727 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ 728 slew-rate = <0>; 729 drive-push-pull; 730 bias-disable; 731 }; 732 }; 733 734 sai4a_sleep_pins_a: sai4a-1 { 735 pins { 736 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ 737 }; 738 }; 739 740 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 741 pins1 { 742 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 743 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 744 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 745 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 746 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 747 slew-rate = <1>; 748 drive-push-pull; 749 bias-disable; 750 }; 751 pins2 { 752 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 753 slew-rate = <2>; 754 drive-push-pull; 755 bias-disable; 756 }; 757 }; 758 759 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { 760 pins1 { 761 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 762 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 763 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 764 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 765 slew-rate = <1>; 766 drive-push-pull; 767 bias-disable; 768 }; 769 pins2 { 770 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 771 slew-rate = <2>; 772 drive-push-pull; 773 bias-disable; 774 }; 775 pins3 { 776 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 777 slew-rate = <1>; 778 drive-open-drain; 779 bias-disable; 780 }; 781 }; 782 783 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { 784 pins { 785 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 786 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 787 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ 788 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 789 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 790 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 791 }; 792 }; 793 794 sdmmc1_dir_pins_a: sdmmc1-dir-0 { 795 pins1 { 796 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 797 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 798 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 799 slew-rate = <1>; 800 drive-push-pull; 801 bias-pull-up; 802 }; 803 pins2{ 804 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 805 bias-pull-up; 806 }; 807 }; 808 809 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { 810 pins { 811 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 812 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ 813 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 814 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 815 }; 816 }; 817 818 sdmmc2_b4_pins_a: sdmmc2-b4-0 { 819 pins1 { 820 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 821 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 822 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 823 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 824 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 825 slew-rate = <1>; 826 drive-push-pull; 827 bias-pull-up; 828 }; 829 pins2 { 830 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 831 slew-rate = <2>; 832 drive-push-pull; 833 bias-pull-up; 834 }; 835 }; 836 837 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { 838 pins1 { 839 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 840 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 841 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 842 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 843 slew-rate = <1>; 844 drive-push-pull; 845 bias-pull-up; 846 }; 847 pins2 { 848 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 849 slew-rate = <2>; 850 drive-push-pull; 851 bias-pull-up; 852 }; 853 pins3 { 854 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 855 slew-rate = <1>; 856 drive-open-drain; 857 bias-pull-up; 858 }; 859 }; 860 861 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { 862 pins { 863 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ 864 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ 865 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ 866 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ 867 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ 868 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ 869 }; 870 }; 871 872 sdmmc2_b4_pins_b: sdmmc2-b4-1 { 873 pins1 { 874 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 875 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 876 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 877 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 878 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 879 slew-rate = <1>; 880 drive-push-pull; 881 bias-disable; 882 }; 883 pins2 { 884 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 885 slew-rate = <2>; 886 drive-push-pull; 887 bias-disable; 888 }; 889 }; 890 891 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { 892 pins1 { 893 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 894 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 895 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 896 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 897 slew-rate = <1>; 898 drive-push-pull; 899 bias-disable; 900 }; 901 pins2 { 902 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 903 slew-rate = <2>; 904 drive-push-pull; 905 bias-disable; 906 }; 907 pins3 { 908 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 909 slew-rate = <1>; 910 drive-open-drain; 911 bias-disable; 912 }; 913 }; 914 915 sdmmc2_d47_pins_a: sdmmc2-d47-0 { 916 pins { 917 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 918 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 919 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 920 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ 921 slew-rate = <1>; 922 drive-push-pull; 923 bias-pull-up; 924 }; 925 }; 926 927 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { 928 pins { 929 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 930 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 931 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 932 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ 933 }; 934 }; 935 936 sdmmc3_b4_pins_a: sdmmc3-b4-0 { 937 pins1 { 938 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 939 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 940 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 941 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 942 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ 943 slew-rate = <1>; 944 drive-push-pull; 945 bias-pull-up; 946 }; 947 pins2 { 948 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 949 slew-rate = <2>; 950 drive-push-pull; 951 bias-pull-up; 952 }; 953 }; 954 955 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { 956 pins1 { 957 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 958 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 959 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 960 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 961 slew-rate = <1>; 962 drive-push-pull; 963 bias-pull-up; 964 }; 965 pins2 { 966 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 967 slew-rate = <2>; 968 drive-push-pull; 969 bias-pull-up; 970 }; 971 pins3 { 972 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ 973 slew-rate = <1>; 974 drive-open-drain; 975 bias-pull-up; 976 }; 977 }; 978 979 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { 980 pins { 981 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 982 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 983 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ 984 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 985 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 986 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ 987 }; 988 }; 989 990 spdifrx_pins_a: spdifrx-0 { 991 pins { 992 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ 993 bias-disable; 994 }; 995 }; 996 997 spdifrx_sleep_pins_a: spdifrx-1 { 998 pins { 999 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ 1000 }; 1001 }; 1002 1003 uart4_pins_a: uart4-0 { 1004 pins1 { 1005 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 1006 bias-disable; 1007 drive-push-pull; 1008 slew-rate = <0>; 1009 }; 1010 pins2 { 1011 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1012 bias-disable; 1013 }; 1014 }; 1015 1016 uart4_pins_b: uart4-1 { 1017 pins1 { 1018 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ 1019 bias-disable; 1020 drive-push-pull; 1021 slew-rate = <0>; 1022 }; 1023 pins2 { 1024 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1025 bias-disable; 1026 }; 1027 }; 1028 1029 uart7_pins_a: uart7-0 { 1030 pins1 { 1031 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */ 1032 bias-disable; 1033 drive-push-pull; 1034 slew-rate = <0>; 1035 }; 1036 pins2 { 1037 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */ 1038 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */ 1039 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */ 1040 bias-disable; 1041 }; 1042 }; 1043}; 1044 1045&pinctrl_z { 1046 i2c2_pins_b2: i2c2-0 { 1047 pins { 1048 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ 1049 bias-disable; 1050 drive-open-drain; 1051 slew-rate = <0>; 1052 }; 1053 }; 1054 1055 i2c2_pins_sleep_b2: i2c2-1 { 1056 pins { 1057 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ 1058 }; 1059 }; 1060 1061 i2c4_pins_a: i2c4-0 { 1062 pins { 1063 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ 1064 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ 1065 bias-disable; 1066 drive-open-drain; 1067 slew-rate = <0>; 1068 }; 1069 }; 1070 1071 i2c4_pins_sleep_a: i2c4-1 { 1072 pins { 1073 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ 1074 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ 1075 }; 1076 }; 1077 1078 spi1_pins_a: spi1-0 { 1079 pins1 { 1080 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ 1081 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ 1082 bias-disable; 1083 drive-push-pull; 1084 slew-rate = <1>; 1085 }; 1086 1087 pins2 { 1088 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ 1089 bias-disable; 1090 }; 1091 }; 1092}; 1093