1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22		};
23	};
24
25	psci {
26		compatible = "arm,psci-1.0";
27		method = "smc";
28	};
29
30	intc: interrupt-controller@a0021000 {
31		compatible = "arm,cortex-a7-gic";
32		#interrupt-cells = <3>;
33		interrupt-controller;
34		reg = <0xa0021000 0x1000>,
35		      <0xa0022000 0x2000>;
36	};
37
38	timer {
39		compatible = "arm,armv7-timer";
40		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
41			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
42			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
43			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
44		interrupt-parent = <&intc>;
45	};
46
47	clocks {
48		clk_hse: clk-hse {
49			#clock-cells = <0>;
50			compatible = "fixed-clock";
51			clock-frequency = <24000000>;
52		};
53
54		clk_hsi: clk-hsi {
55			#clock-cells = <0>;
56			compatible = "fixed-clock";
57			clock-frequency = <64000000>;
58		};
59
60		clk_lse: clk-lse {
61			#clock-cells = <0>;
62			compatible = "fixed-clock";
63			clock-frequency = <32768>;
64		};
65
66		clk_lsi: clk-lsi {
67			#clock-cells = <0>;
68			compatible = "fixed-clock";
69			clock-frequency = <32000>;
70		};
71
72		clk_csi: clk-csi {
73			#clock-cells = <0>;
74			compatible = "fixed-clock";
75			clock-frequency = <4000000>;
76		};
77	};
78
79	thermal-zones {
80		cpu_thermal: cpu-thermal {
81			polling-delay-passive = <0>;
82			polling-delay = <0>;
83			thermal-sensors = <&dts>;
84
85			trips {
86				cpu_alert1: cpu-alert1 {
87					temperature = <85000>;
88					hysteresis = <0>;
89					type = "passive";
90				};
91
92				cpu-crit {
93					temperature = <120000>;
94					hysteresis = <0>;
95					type = "critical";
96				};
97			};
98
99			cooling-maps {
100			};
101		};
102	};
103
104	booster: regulator-booster {
105		compatible = "st,stm32mp1-booster";
106		st,syscfg = <&syscfg>;
107		status = "disabled";
108	};
109
110	soc {
111		compatible = "simple-bus";
112		#address-cells = <1>;
113		#size-cells = <1>;
114		interrupt-parent = <&intc>;
115		ranges;
116
117		timers2: timer@40000000 {
118			#address-cells = <1>;
119			#size-cells = <0>;
120			compatible = "st,stm32-timers";
121			reg = <0x40000000 0x400>;
122			clocks = <&rcc TIM2_K>;
123			clock-names = "int";
124			dmas = <&dmamux1 18 0x400 0x1>,
125			       <&dmamux1 19 0x400 0x1>,
126			       <&dmamux1 20 0x400 0x1>,
127			       <&dmamux1 21 0x400 0x1>,
128			       <&dmamux1 22 0x400 0x1>;
129			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
130			status = "disabled";
131
132			pwm {
133				compatible = "st,stm32-pwm";
134				#pwm-cells = <3>;
135				status = "disabled";
136			};
137
138			timer@1 {
139				compatible = "st,stm32h7-timer-trigger";
140				reg = <1>;
141				status = "disabled";
142			};
143
144			counter {
145				compatible = "st,stm32-timer-counter";
146				status = "disabled";
147			};
148		};
149
150		timers3: timer@40001000 {
151			#address-cells = <1>;
152			#size-cells = <0>;
153			compatible = "st,stm32-timers";
154			reg = <0x40001000 0x400>;
155			clocks = <&rcc TIM3_K>;
156			clock-names = "int";
157			dmas = <&dmamux1 23 0x400 0x1>,
158			       <&dmamux1 24 0x400 0x1>,
159			       <&dmamux1 25 0x400 0x1>,
160			       <&dmamux1 26 0x400 0x1>,
161			       <&dmamux1 27 0x400 0x1>,
162			       <&dmamux1 28 0x400 0x1>;
163			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
164			status = "disabled";
165
166			pwm {
167				compatible = "st,stm32-pwm";
168				#pwm-cells = <3>;
169				status = "disabled";
170			};
171
172			timer@2 {
173				compatible = "st,stm32h7-timer-trigger";
174				reg = <2>;
175				status = "disabled";
176			};
177
178			counter {
179				compatible = "st,stm32-timer-counter";
180				status = "disabled";
181			};
182		};
183
184		timers4: timer@40002000 {
185			#address-cells = <1>;
186			#size-cells = <0>;
187			compatible = "st,stm32-timers";
188			reg = <0x40002000 0x400>;
189			clocks = <&rcc TIM4_K>;
190			clock-names = "int";
191			dmas = <&dmamux1 29 0x400 0x1>,
192			       <&dmamux1 30 0x400 0x1>,
193			       <&dmamux1 31 0x400 0x1>,
194			       <&dmamux1 32 0x400 0x1>;
195			dma-names = "ch1", "ch2", "ch3", "ch4";
196			status = "disabled";
197
198			pwm {
199				compatible = "st,stm32-pwm";
200				#pwm-cells = <3>;
201				status = "disabled";
202			};
203
204			timer@3 {
205				compatible = "st,stm32h7-timer-trigger";
206				reg = <3>;
207				status = "disabled";
208			};
209
210			counter {
211				compatible = "st,stm32-timer-counter";
212				status = "disabled";
213			};
214		};
215
216		timers5: timer@40003000 {
217			#address-cells = <1>;
218			#size-cells = <0>;
219			compatible = "st,stm32-timers";
220			reg = <0x40003000 0x400>;
221			clocks = <&rcc TIM5_K>;
222			clock-names = "int";
223			dmas = <&dmamux1 55 0x400 0x1>,
224			       <&dmamux1 56 0x400 0x1>,
225			       <&dmamux1 57 0x400 0x1>,
226			       <&dmamux1 58 0x400 0x1>,
227			       <&dmamux1 59 0x400 0x1>,
228			       <&dmamux1 60 0x400 0x1>;
229			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
230			status = "disabled";
231
232			pwm {
233				compatible = "st,stm32-pwm";
234				#pwm-cells = <3>;
235				status = "disabled";
236			};
237
238			timer@4 {
239				compatible = "st,stm32h7-timer-trigger";
240				reg = <4>;
241				status = "disabled";
242			};
243
244			counter {
245				compatible = "st,stm32-timer-counter";
246				status = "disabled";
247			};
248		};
249
250		timers6: timer@40004000 {
251			#address-cells = <1>;
252			#size-cells = <0>;
253			compatible = "st,stm32-timers";
254			reg = <0x40004000 0x400>;
255			clocks = <&rcc TIM6_K>;
256			clock-names = "int";
257			dmas = <&dmamux1 69 0x400 0x1>;
258			dma-names = "up";
259			status = "disabled";
260
261			timer@5 {
262				compatible = "st,stm32h7-timer-trigger";
263				reg = <5>;
264				status = "disabled";
265			};
266		};
267
268		timers7: timer@40005000 {
269			#address-cells = <1>;
270			#size-cells = <0>;
271			compatible = "st,stm32-timers";
272			reg = <0x40005000 0x400>;
273			clocks = <&rcc TIM7_K>;
274			clock-names = "int";
275			dmas = <&dmamux1 70 0x400 0x1>;
276			dma-names = "up";
277			status = "disabled";
278
279			timer@6 {
280				compatible = "st,stm32h7-timer-trigger";
281				reg = <6>;
282				status = "disabled";
283			};
284		};
285
286		timers12: timer@40006000 {
287			#address-cells = <1>;
288			#size-cells = <0>;
289			compatible = "st,stm32-timers";
290			reg = <0x40006000 0x400>;
291			clocks = <&rcc TIM12_K>;
292			clock-names = "int";
293			status = "disabled";
294
295			pwm {
296				compatible = "st,stm32-pwm";
297				#pwm-cells = <3>;
298				status = "disabled";
299			};
300
301			timer@11 {
302				compatible = "st,stm32h7-timer-trigger";
303				reg = <11>;
304				status = "disabled";
305			};
306		};
307
308		timers13: timer@40007000 {
309			#address-cells = <1>;
310			#size-cells = <0>;
311			compatible = "st,stm32-timers";
312			reg = <0x40007000 0x400>;
313			clocks = <&rcc TIM13_K>;
314			clock-names = "int";
315			status = "disabled";
316
317			pwm {
318				compatible = "st,stm32-pwm";
319				#pwm-cells = <3>;
320				status = "disabled";
321			};
322
323			timer@12 {
324				compatible = "st,stm32h7-timer-trigger";
325				reg = <12>;
326				status = "disabled";
327			};
328		};
329
330		timers14: timer@40008000 {
331			#address-cells = <1>;
332			#size-cells = <0>;
333			compatible = "st,stm32-timers";
334			reg = <0x40008000 0x400>;
335			clocks = <&rcc TIM14_K>;
336			clock-names = "int";
337			status = "disabled";
338
339			pwm {
340				compatible = "st,stm32-pwm";
341				#pwm-cells = <3>;
342				status = "disabled";
343			};
344
345			timer@13 {
346				compatible = "st,stm32h7-timer-trigger";
347				reg = <13>;
348				status = "disabled";
349			};
350		};
351
352		lptimer1: timer@40009000 {
353			#address-cells = <1>;
354			#size-cells = <0>;
355			compatible = "st,stm32-lptimer";
356			reg = <0x40009000 0x400>;
357			clocks = <&rcc LPTIM1_K>;
358			clock-names = "mux";
359			status = "disabled";
360
361			pwm {
362				compatible = "st,stm32-pwm-lp";
363				#pwm-cells = <3>;
364				status = "disabled";
365			};
366
367			trigger@0 {
368				compatible = "st,stm32-lptimer-trigger";
369				reg = <0>;
370				status = "disabled";
371			};
372
373			counter {
374				compatible = "st,stm32-lptimer-counter";
375				status = "disabled";
376			};
377		};
378
379		spi2: spi@4000b000 {
380			#address-cells = <1>;
381			#size-cells = <0>;
382			compatible = "st,stm32h7-spi";
383			reg = <0x4000b000 0x400>;
384			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
385			clocks = <&rcc SPI2_K>;
386			resets = <&rcc SPI2_R>;
387			dmas = <&dmamux1 39 0x400 0x05>,
388			       <&dmamux1 40 0x400 0x05>;
389			dma-names = "rx", "tx";
390			status = "disabled";
391		};
392
393		i2s2: audio-controller@4000b000 {
394			compatible = "st,stm32h7-i2s";
395			#sound-dai-cells = <0>;
396			reg = <0x4000b000 0x400>;
397			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
398			dmas = <&dmamux1 39 0x400 0x01>,
399			       <&dmamux1 40 0x400 0x01>;
400			dma-names = "rx", "tx";
401			status = "disabled";
402		};
403
404		spi3: spi@4000c000 {
405			#address-cells = <1>;
406			#size-cells = <0>;
407			compatible = "st,stm32h7-spi";
408			reg = <0x4000c000 0x400>;
409			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
410			clocks = <&rcc SPI3_K>;
411			resets = <&rcc SPI3_R>;
412			dmas = <&dmamux1 61 0x400 0x05>,
413			       <&dmamux1 62 0x400 0x05>;
414			dma-names = "rx", "tx";
415			status = "disabled";
416		};
417
418		i2s3: audio-controller@4000c000 {
419			compatible = "st,stm32h7-i2s";
420			#sound-dai-cells = <0>;
421			reg = <0x4000c000 0x400>;
422			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
423			dmas = <&dmamux1 61 0x400 0x01>,
424			       <&dmamux1 62 0x400 0x01>;
425			dma-names = "rx", "tx";
426			status = "disabled";
427		};
428
429		spdifrx: audio-controller@4000d000 {
430			compatible = "st,stm32h7-spdifrx";
431			#sound-dai-cells = <0>;
432			reg = <0x4000d000 0x400>;
433			clocks = <&rcc SPDIF_K>;
434			clock-names = "kclk";
435			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
436			dmas = <&dmamux1 93 0x400 0x01>,
437			       <&dmamux1 94 0x400 0x01>;
438			dma-names = "rx", "rx-ctrl";
439			status = "disabled";
440		};
441
442		usart2: serial@4000e000 {
443			compatible = "st,stm32h7-uart";
444			reg = <0x4000e000 0x400>;
445			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
446			clocks = <&rcc USART2_K>;
447			status = "disabled";
448		};
449
450		usart3: serial@4000f000 {
451			compatible = "st,stm32h7-uart";
452			reg = <0x4000f000 0x400>;
453			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
454			clocks = <&rcc USART3_K>;
455			status = "disabled";
456		};
457
458		uart4: serial@40010000 {
459			compatible = "st,stm32h7-uart";
460			reg = <0x40010000 0x400>;
461			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
462			clocks = <&rcc UART4_K>;
463			status = "disabled";
464		};
465
466		uart5: serial@40011000 {
467			compatible = "st,stm32h7-uart";
468			reg = <0x40011000 0x400>;
469			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
470			clocks = <&rcc UART5_K>;
471			status = "disabled";
472		};
473
474		i2c1: i2c@40012000 {
475			compatible = "st,stm32f7-i2c";
476			reg = <0x40012000 0x400>;
477			interrupt-names = "event", "error";
478			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
479				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
480			clocks = <&rcc I2C1_K>;
481			resets = <&rcc I2C1_R>;
482			#address-cells = <1>;
483			#size-cells = <0>;
484			status = "disabled";
485		};
486
487		i2c2: i2c@40013000 {
488			compatible = "st,stm32f7-i2c";
489			reg = <0x40013000 0x400>;
490			interrupt-names = "event", "error";
491			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
492				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
493			clocks = <&rcc I2C2_K>;
494			resets = <&rcc I2C2_R>;
495			#address-cells = <1>;
496			#size-cells = <0>;
497			status = "disabled";
498		};
499
500		i2c3: i2c@40014000 {
501			compatible = "st,stm32f7-i2c";
502			reg = <0x40014000 0x400>;
503			interrupt-names = "event", "error";
504			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
505				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
506			clocks = <&rcc I2C3_K>;
507			resets = <&rcc I2C3_R>;
508			#address-cells = <1>;
509			#size-cells = <0>;
510			status = "disabled";
511		};
512
513		i2c5: i2c@40015000 {
514			compatible = "st,stm32f7-i2c";
515			reg = <0x40015000 0x400>;
516			interrupt-names = "event", "error";
517			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
518				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
519			clocks = <&rcc I2C5_K>;
520			resets = <&rcc I2C5_R>;
521			#address-cells = <1>;
522			#size-cells = <0>;
523			status = "disabled";
524		};
525
526		cec: cec@40016000 {
527			compatible = "st,stm32-cec";
528			reg = <0x40016000 0x400>;
529			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
530			clocks = <&rcc CEC_K>, <&clk_lse>;
531			clock-names = "cec", "hdmi-cec";
532			status = "disabled";
533		};
534
535		dac: dac@40017000 {
536			compatible = "st,stm32h7-dac-core";
537			reg = <0x40017000 0x400>;
538			clocks = <&rcc DAC12>;
539			clock-names = "pclk";
540			#address-cells = <1>;
541			#size-cells = <0>;
542			status = "disabled";
543
544			dac1: dac@1 {
545				compatible = "st,stm32-dac";
546				#io-channels-cells = <1>;
547				reg = <1>;
548				status = "disabled";
549			};
550
551			dac2: dac@2 {
552				compatible = "st,stm32-dac";
553				#io-channels-cells = <1>;
554				reg = <2>;
555				status = "disabled";
556			};
557		};
558
559		uart7: serial@40018000 {
560			compatible = "st,stm32h7-uart";
561			reg = <0x40018000 0x400>;
562			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
563			clocks = <&rcc UART7_K>;
564			status = "disabled";
565		};
566
567		uart8: serial@40019000 {
568			compatible = "st,stm32h7-uart";
569			reg = <0x40019000 0x400>;
570			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
571			clocks = <&rcc UART8_K>;
572			status = "disabled";
573		};
574
575		timers1: timer@44000000 {
576			#address-cells = <1>;
577			#size-cells = <0>;
578			compatible = "st,stm32-timers";
579			reg = <0x44000000 0x400>;
580			clocks = <&rcc TIM1_K>;
581			clock-names = "int";
582			dmas = <&dmamux1 11 0x400 0x1>,
583			       <&dmamux1 12 0x400 0x1>,
584			       <&dmamux1 13 0x400 0x1>,
585			       <&dmamux1 14 0x400 0x1>,
586			       <&dmamux1 15 0x400 0x1>,
587			       <&dmamux1 16 0x400 0x1>,
588			       <&dmamux1 17 0x400 0x1>;
589			dma-names = "ch1", "ch2", "ch3", "ch4",
590				    "up", "trig", "com";
591			status = "disabled";
592
593			pwm {
594				compatible = "st,stm32-pwm";
595				#pwm-cells = <3>;
596				status = "disabled";
597			};
598
599			timer@0 {
600				compatible = "st,stm32h7-timer-trigger";
601				reg = <0>;
602				status = "disabled";
603			};
604
605			counter {
606				compatible = "st,stm32-timer-counter";
607				status = "disabled";
608			};
609		};
610
611		timers8: timer@44001000 {
612			#address-cells = <1>;
613			#size-cells = <0>;
614			compatible = "st,stm32-timers";
615			reg = <0x44001000 0x400>;
616			clocks = <&rcc TIM8_K>;
617			clock-names = "int";
618			dmas = <&dmamux1 47 0x400 0x1>,
619			       <&dmamux1 48 0x400 0x1>,
620			       <&dmamux1 49 0x400 0x1>,
621			       <&dmamux1 50 0x400 0x1>,
622			       <&dmamux1 51 0x400 0x1>,
623			       <&dmamux1 52 0x400 0x1>,
624			       <&dmamux1 53 0x400 0x1>;
625			dma-names = "ch1", "ch2", "ch3", "ch4",
626				    "up", "trig", "com";
627			status = "disabled";
628
629			pwm {
630				compatible = "st,stm32-pwm";
631				#pwm-cells = <3>;
632				status = "disabled";
633			};
634
635			timer@7 {
636				compatible = "st,stm32h7-timer-trigger";
637				reg = <7>;
638				status = "disabled";
639			};
640
641			counter {
642				compatible = "st,stm32-timer-counter";
643				status = "disabled";
644			};
645		};
646
647		usart6: serial@44003000 {
648			compatible = "st,stm32h7-uart";
649			reg = <0x44003000 0x400>;
650			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
651			clocks = <&rcc USART6_K>;
652			status = "disabled";
653		};
654
655		spi1: spi@44004000 {
656			#address-cells = <1>;
657			#size-cells = <0>;
658			compatible = "st,stm32h7-spi";
659			reg = <0x44004000 0x400>;
660			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
661			clocks = <&rcc SPI1_K>;
662			resets = <&rcc SPI1_R>;
663			dmas = <&dmamux1 37 0x400 0x05>,
664			       <&dmamux1 38 0x400 0x05>;
665			dma-names = "rx", "tx";
666			status = "disabled";
667		};
668
669		i2s1: audio-controller@44004000 {
670			compatible = "st,stm32h7-i2s";
671			#sound-dai-cells = <0>;
672			reg = <0x44004000 0x400>;
673			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
674			dmas = <&dmamux1 37 0x400 0x01>,
675			       <&dmamux1 38 0x400 0x01>;
676			dma-names = "rx", "tx";
677			status = "disabled";
678		};
679
680		spi4: spi@44005000 {
681			#address-cells = <1>;
682			#size-cells = <0>;
683			compatible = "st,stm32h7-spi";
684			reg = <0x44005000 0x400>;
685			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
686			clocks = <&rcc SPI4_K>;
687			resets = <&rcc SPI4_R>;
688			dmas = <&dmamux1 83 0x400 0x05>,
689			       <&dmamux1 84 0x400 0x05>;
690			dma-names = "rx", "tx";
691			status = "disabled";
692		};
693
694		timers15: timer@44006000 {
695			#address-cells = <1>;
696			#size-cells = <0>;
697			compatible = "st,stm32-timers";
698			reg = <0x44006000 0x400>;
699			clocks = <&rcc TIM15_K>;
700			clock-names = "int";
701			dmas = <&dmamux1 105 0x400 0x1>,
702			       <&dmamux1 106 0x400 0x1>,
703			       <&dmamux1 107 0x400 0x1>,
704			       <&dmamux1 108 0x400 0x1>;
705			dma-names = "ch1", "up", "trig", "com";
706			status = "disabled";
707
708			pwm {
709				compatible = "st,stm32-pwm";
710				#pwm-cells = <3>;
711				status = "disabled";
712			};
713
714			timer@14 {
715				compatible = "st,stm32h7-timer-trigger";
716				reg = <14>;
717				status = "disabled";
718			};
719		};
720
721		timers16: timer@44007000 {
722			#address-cells = <1>;
723			#size-cells = <0>;
724			compatible = "st,stm32-timers";
725			reg = <0x44007000 0x400>;
726			clocks = <&rcc TIM16_K>;
727			clock-names = "int";
728			dmas = <&dmamux1 109 0x400 0x1>,
729			       <&dmamux1 110 0x400 0x1>;
730			dma-names = "ch1", "up";
731			status = "disabled";
732
733			pwm {
734				compatible = "st,stm32-pwm";
735				#pwm-cells = <3>;
736				status = "disabled";
737			};
738			timer@15 {
739				compatible = "st,stm32h7-timer-trigger";
740				reg = <15>;
741				status = "disabled";
742			};
743		};
744
745		timers17: timer@44008000 {
746			#address-cells = <1>;
747			#size-cells = <0>;
748			compatible = "st,stm32-timers";
749			reg = <0x44008000 0x400>;
750			clocks = <&rcc TIM17_K>;
751			clock-names = "int";
752			dmas = <&dmamux1 111 0x400 0x1>,
753			       <&dmamux1 112 0x400 0x1>;
754			dma-names = "ch1", "up";
755			status = "disabled";
756
757			pwm {
758				compatible = "st,stm32-pwm";
759				#pwm-cells = <3>;
760				status = "disabled";
761			};
762
763			timer@16 {
764				compatible = "st,stm32h7-timer-trigger";
765				reg = <16>;
766				status = "disabled";
767			};
768		};
769
770		spi5: spi@44009000 {
771			#address-cells = <1>;
772			#size-cells = <0>;
773			compatible = "st,stm32h7-spi";
774			reg = <0x44009000 0x400>;
775			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
776			clocks = <&rcc SPI5_K>;
777			resets = <&rcc SPI5_R>;
778			dmas = <&dmamux1 85 0x400 0x05>,
779			       <&dmamux1 86 0x400 0x05>;
780			dma-names = "rx", "tx";
781			status = "disabled";
782		};
783
784		sai1: sai@4400a000 {
785			compatible = "st,stm32h7-sai";
786			#address-cells = <1>;
787			#size-cells = <1>;
788			ranges = <0 0x4400a000 0x400>;
789			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
790			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
791			resets = <&rcc SAI1_R>;
792			status = "disabled";
793
794			sai1a: audio-controller@4400a004 {
795				#sound-dai-cells = <0>;
796
797				compatible = "st,stm32-sai-sub-a";
798				reg = <0x4 0x1c>;
799				clocks = <&rcc SAI1_K>;
800				clock-names = "sai_ck";
801				dmas = <&dmamux1 87 0x400 0x01>;
802				status = "disabled";
803			};
804
805			sai1b: audio-controller@4400a024 {
806				#sound-dai-cells = <0>;
807				compatible = "st,stm32-sai-sub-b";
808				reg = <0x24 0x1c>;
809				clocks = <&rcc SAI1_K>;
810				clock-names = "sai_ck";
811				dmas = <&dmamux1 88 0x400 0x01>;
812				status = "disabled";
813			};
814		};
815
816		sai2: sai@4400b000 {
817			compatible = "st,stm32h7-sai";
818			#address-cells = <1>;
819			#size-cells = <1>;
820			ranges = <0 0x4400b000 0x400>;
821			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
822			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
823			resets = <&rcc SAI2_R>;
824			status = "disabled";
825
826			sai2a: audio-controller@4400b004 {
827				#sound-dai-cells = <0>;
828				compatible = "st,stm32-sai-sub-a";
829				reg = <0x4 0x1c>;
830				clocks = <&rcc SAI2_K>;
831				clock-names = "sai_ck";
832				dmas = <&dmamux1 89 0x400 0x01>;
833				status = "disabled";
834			};
835
836			sai2b: audio-controller@4400b024 {
837				#sound-dai-cells = <0>;
838				compatible = "st,stm32-sai-sub-b";
839				reg = <0x24 0x1c>;
840				clocks = <&rcc SAI2_K>;
841				clock-names = "sai_ck";
842				dmas = <&dmamux1 90 0x400 0x01>;
843				status = "disabled";
844			};
845		};
846
847		sai3: sai@4400c000 {
848			compatible = "st,stm32h7-sai";
849			#address-cells = <1>;
850			#size-cells = <1>;
851			ranges = <0 0x4400c000 0x400>;
852			reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
853			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
854			resets = <&rcc SAI3_R>;
855			status = "disabled";
856
857			sai3a: audio-controller@4400c004 {
858				#sound-dai-cells = <0>;
859				compatible = "st,stm32-sai-sub-a";
860				reg = <0x04 0x1c>;
861				clocks = <&rcc SAI3_K>;
862				clock-names = "sai_ck";
863				dmas = <&dmamux1 113 0x400 0x01>;
864				status = "disabled";
865			};
866
867			sai3b: audio-controller@4400c024 {
868				#sound-dai-cells = <0>;
869				compatible = "st,stm32-sai-sub-b";
870				reg = <0x24 0x1c>;
871				clocks = <&rcc SAI3_K>;
872				clock-names = "sai_ck";
873				dmas = <&dmamux1 114 0x400 0x01>;
874				status = "disabled";
875			};
876		};
877
878		dfsdm: dfsdm@4400d000 {
879			compatible = "st,stm32mp1-dfsdm";
880			reg = <0x4400d000 0x800>;
881			clocks = <&rcc DFSDM_K>;
882			clock-names = "dfsdm";
883			#address-cells = <1>;
884			#size-cells = <0>;
885			status = "disabled";
886
887			dfsdm0: filter@0 {
888				compatible = "st,stm32-dfsdm-adc";
889				#io-channel-cells = <1>;
890				reg = <0>;
891				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
892				dmas = <&dmamux1 101 0x400 0x01>;
893				dma-names = "rx";
894				status = "disabled";
895			};
896
897			dfsdm1: filter@1 {
898				compatible = "st,stm32-dfsdm-adc";
899				#io-channel-cells = <1>;
900				reg = <1>;
901				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
902				dmas = <&dmamux1 102 0x400 0x01>;
903				dma-names = "rx";
904				status = "disabled";
905			};
906
907			dfsdm2: filter@2 {
908				compatible = "st,stm32-dfsdm-adc";
909				#io-channel-cells = <1>;
910				reg = <2>;
911				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
912				dmas = <&dmamux1 103 0x400 0x01>;
913				dma-names = "rx";
914				status = "disabled";
915			};
916
917			dfsdm3: filter@3 {
918				compatible = "st,stm32-dfsdm-adc";
919				#io-channel-cells = <1>;
920				reg = <3>;
921				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
922				dmas = <&dmamux1 104 0x400 0x01>;
923				dma-names = "rx";
924				status = "disabled";
925			};
926
927			dfsdm4: filter@4 {
928				compatible = "st,stm32-dfsdm-adc";
929				#io-channel-cells = <1>;
930				reg = <4>;
931				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
932				dmas = <&dmamux1 91 0x400 0x01>;
933				dma-names = "rx";
934				status = "disabled";
935			};
936
937			dfsdm5: filter@5 {
938				compatible = "st,stm32-dfsdm-adc";
939				#io-channel-cells = <1>;
940				reg = <5>;
941				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
942				dmas = <&dmamux1 92 0x400 0x01>;
943				dma-names = "rx";
944				status = "disabled";
945			};
946		};
947
948		dma1: dma-controller@48000000 {
949			compatible = "st,stm32-dma";
950			reg = <0x48000000 0x400>;
951			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
952				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
953				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
954				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
955				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
956				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
957				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
958				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
959			clocks = <&rcc DMA1>;
960			#dma-cells = <4>;
961			st,mem2mem;
962			dma-requests = <8>;
963		};
964
965		dma2: dma-controller@48001000 {
966			compatible = "st,stm32-dma";
967			reg = <0x48001000 0x400>;
968			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
969				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
970				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
971				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
972				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
973				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
974				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
975				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
976			clocks = <&rcc DMA2>;
977			#dma-cells = <4>;
978			st,mem2mem;
979			dma-requests = <8>;
980		};
981
982		dmamux1: dma-router@48002000 {
983			compatible = "st,stm32h7-dmamux";
984			reg = <0x48002000 0x1c>;
985			#dma-cells = <3>;
986			dma-requests = <128>;
987			dma-masters = <&dma1 &dma2>;
988			dma-channels = <16>;
989			clocks = <&rcc DMAMUX>;
990		};
991
992		adc: adc@48003000 {
993			compatible = "st,stm32mp1-adc-core";
994			reg = <0x48003000 0x400>;
995			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
996				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
997			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
998			clock-names = "bus", "adc";
999			interrupt-controller;
1000			st,syscfg = <&syscfg>;
1001			#interrupt-cells = <1>;
1002			#address-cells = <1>;
1003			#size-cells = <0>;
1004			status = "disabled";
1005
1006			adc1: adc@0 {
1007				compatible = "st,stm32mp1-adc";
1008				#io-channel-cells = <1>;
1009				reg = <0x0>;
1010				interrupt-parent = <&adc>;
1011				interrupts = <0>;
1012				dmas = <&dmamux1 9 0x400 0x01>;
1013				dma-names = "rx";
1014				status = "disabled";
1015			};
1016
1017			adc2: adc@100 {
1018				compatible = "st,stm32mp1-adc";
1019				#io-channel-cells = <1>;
1020				reg = <0x100>;
1021				interrupt-parent = <&adc>;
1022				interrupts = <1>;
1023				dmas = <&dmamux1 10 0x400 0x01>;
1024				dma-names = "rx";
1025				status = "disabled";
1026			};
1027		};
1028
1029		sdmmc3: sdmmc@48004000 {
1030			compatible = "arm,pl18x", "arm,primecell";
1031			arm,primecell-periphid = <0x10153180>;
1032			reg = <0x48004000 0x400>;
1033			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1034			interrupt-names = "cmd_irq";
1035			clocks = <&rcc SDMMC3_K>;
1036			clock-names = "apb_pclk";
1037			resets = <&rcc SDMMC3_R>;
1038			cap-sd-highspeed;
1039			cap-mmc-highspeed;
1040			max-frequency = <120000000>;
1041			status = "disabled";
1042		};
1043
1044		usbotg_hs: usb-otg@49000000 {
1045			compatible = "snps,dwc2";
1046			reg = <0x49000000 0x10000>;
1047			clocks = <&rcc USBO_K>;
1048			clock-names = "otg";
1049			resets = <&rcc USBO_R>;
1050			reset-names = "dwc2";
1051			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1052			g-rx-fifo-size = <256>;
1053			g-np-tx-fifo-size = <32>;
1054			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1055			dr_mode = "otg";
1056			status = "disabled";
1057		};
1058
1059		ipcc: mailbox@4c001000 {
1060			compatible = "st,stm32mp1-ipcc";
1061			#mbox-cells = <1>;
1062			reg = <0x4c001000 0x400>;
1063			st,proc-id = <0>;
1064			interrupts-extended =
1065				<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1066				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1067				<&exti 61 1>;
1068			interrupt-names = "rx", "tx", "wakeup";
1069			clocks = <&rcc IPCC>;
1070			wakeup-source;
1071			status = "disabled";
1072		};
1073
1074		dcmi: dcmi@4c006000 {
1075			compatible = "st,stm32-dcmi";
1076			reg = <0x4c006000 0x400>;
1077			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1078			resets = <&rcc CAMITF_R>;
1079			clocks = <&rcc DCMI>;
1080			clock-names = "mclk";
1081			dmas = <&dmamux1 75 0x400 0x0d>;
1082			dma-names = "tx";
1083			status = "disabled";
1084		};
1085
1086		rcc: rcc@50000000 {
1087			compatible = "st,stm32mp1-rcc", "syscon";
1088			reg = <0x50000000 0x1000>;
1089			#clock-cells = <1>;
1090			#reset-cells = <1>;
1091		};
1092
1093		pwr_regulators: pwr@50001000 {
1094			compatible = "st,stm32mp1,pwr-reg";
1095			reg = <0x50001000 0x10>;
1096
1097			reg11: reg11 {
1098				regulator-name = "reg11";
1099				regulator-min-microvolt = <1100000>;
1100				regulator-max-microvolt = <1100000>;
1101			};
1102
1103			reg18: reg18 {
1104				regulator-name = "reg18";
1105				regulator-min-microvolt = <1800000>;
1106				regulator-max-microvolt = <1800000>;
1107			};
1108
1109			usb33: usb33 {
1110				regulator-name = "usb33";
1111				regulator-min-microvolt = <3300000>;
1112				regulator-max-microvolt = <3300000>;
1113			};
1114		};
1115
1116		exti: interrupt-controller@5000d000 {
1117			compatible = "st,stm32mp1-exti", "syscon";
1118			interrupt-controller;
1119			#interrupt-cells = <2>;
1120			reg = <0x5000d000 0x400>;
1121		};
1122
1123		syscfg: syscon@50020000 {
1124			compatible = "st,stm32mp157-syscfg", "syscon";
1125			reg = <0x50020000 0x400>;
1126			clocks = <&rcc SYSCFG>;
1127		};
1128
1129		lptimer2: timer@50021000 {
1130			#address-cells = <1>;
1131			#size-cells = <0>;
1132			compatible = "st,stm32-lptimer";
1133			reg = <0x50021000 0x400>;
1134			clocks = <&rcc LPTIM2_K>;
1135			clock-names = "mux";
1136			status = "disabled";
1137
1138			pwm {
1139				compatible = "st,stm32-pwm-lp";
1140				#pwm-cells = <3>;
1141				status = "disabled";
1142			};
1143
1144			trigger@1 {
1145				compatible = "st,stm32-lptimer-trigger";
1146				reg = <1>;
1147				status = "disabled";
1148			};
1149
1150			counter {
1151				compatible = "st,stm32-lptimer-counter";
1152				status = "disabled";
1153			};
1154		};
1155
1156		lptimer3: timer@50022000 {
1157			#address-cells = <1>;
1158			#size-cells = <0>;
1159			compatible = "st,stm32-lptimer";
1160			reg = <0x50022000 0x400>;
1161			clocks = <&rcc LPTIM3_K>;
1162			clock-names = "mux";
1163			status = "disabled";
1164
1165			pwm {
1166				compatible = "st,stm32-pwm-lp";
1167				#pwm-cells = <3>;
1168				status = "disabled";
1169			};
1170
1171			trigger@2 {
1172				compatible = "st,stm32-lptimer-trigger";
1173				reg = <2>;
1174				status = "disabled";
1175			};
1176		};
1177
1178		lptimer4: timer@50023000 {
1179			compatible = "st,stm32-lptimer";
1180			reg = <0x50023000 0x400>;
1181			clocks = <&rcc LPTIM4_K>;
1182			clock-names = "mux";
1183			status = "disabled";
1184
1185			pwm {
1186				compatible = "st,stm32-pwm-lp";
1187				#pwm-cells = <3>;
1188				status = "disabled";
1189			};
1190		};
1191
1192		lptimer5: timer@50024000 {
1193			compatible = "st,stm32-lptimer";
1194			reg = <0x50024000 0x400>;
1195			clocks = <&rcc LPTIM5_K>;
1196			clock-names = "mux";
1197			status = "disabled";
1198
1199			pwm {
1200				compatible = "st,stm32-pwm-lp";
1201				#pwm-cells = <3>;
1202				status = "disabled";
1203			};
1204		};
1205
1206		vrefbuf: vrefbuf@50025000 {
1207			compatible = "st,stm32-vrefbuf";
1208			reg = <0x50025000 0x8>;
1209			regulator-min-microvolt = <1500000>;
1210			regulator-max-microvolt = <2500000>;
1211			clocks = <&rcc VREF>;
1212			status = "disabled";
1213		};
1214
1215		sai4: sai@50027000 {
1216			compatible = "st,stm32h7-sai";
1217			#address-cells = <1>;
1218			#size-cells = <1>;
1219			ranges = <0 0x50027000 0x400>;
1220			reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1221			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1222			resets = <&rcc SAI4_R>;
1223			status = "disabled";
1224
1225			sai4a: audio-controller@50027004 {
1226				#sound-dai-cells = <0>;
1227				compatible = "st,stm32-sai-sub-a";
1228				reg = <0x04 0x1c>;
1229				clocks = <&rcc SAI4_K>;
1230				clock-names = "sai_ck";
1231				dmas = <&dmamux1 99 0x400 0x01>;
1232				status = "disabled";
1233			};
1234
1235			sai4b: audio-controller@50027024 {
1236				#sound-dai-cells = <0>;
1237				compatible = "st,stm32-sai-sub-b";
1238				reg = <0x24 0x1c>;
1239				clocks = <&rcc SAI4_K>;
1240				clock-names = "sai_ck";
1241				dmas = <&dmamux1 100 0x400 0x01>;
1242				status = "disabled";
1243			};
1244		};
1245
1246		dts: thermal@50028000 {
1247			compatible = "st,stm32-thermal";
1248			reg = <0x50028000 0x100>;
1249			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1250			clocks = <&rcc TMPSENS>;
1251			clock-names = "pclk";
1252			#thermal-sensor-cells = <0>;
1253			status = "disabled";
1254		};
1255
1256		hash1: hash@54002000 {
1257			compatible = "st,stm32f756-hash";
1258			reg = <0x54002000 0x400>;
1259			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1260			clocks = <&rcc HASH1>;
1261			resets = <&rcc HASH1_R>;
1262			dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1263			dma-names = "in";
1264			dma-maxburst = <2>;
1265			status = "disabled";
1266		};
1267
1268		rng1: rng@54003000 {
1269			compatible = "st,stm32-rng";
1270			reg = <0x54003000 0x400>;
1271			clocks = <&rcc RNG1_K>;
1272			resets = <&rcc RNG1_R>;
1273			status = "disabled";
1274		};
1275
1276		mdma1: dma-controller@58000000 {
1277			compatible = "st,stm32h7-mdma";
1278			reg = <0x58000000 0x1000>;
1279			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1280			clocks = <&rcc MDMA>;
1281			#dma-cells = <5>;
1282			dma-channels = <32>;
1283			dma-requests = <48>;
1284		};
1285
1286		fmc: nand-controller@58002000 {
1287			compatible = "st,stm32mp15-fmc2";
1288			reg = <0x58002000 0x1000>,
1289			      <0x80000000 0x1000>,
1290			      <0x88010000 0x1000>,
1291			      <0x88020000 0x1000>,
1292			      <0x81000000 0x1000>,
1293			      <0x89010000 0x1000>,
1294			      <0x89020000 0x1000>;
1295			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1296			dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1297			       <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1298			       <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1299			dma-names = "tx", "rx", "ecc";
1300			clocks = <&rcc FMC_K>;
1301			resets = <&rcc FMC_R>;
1302			status = "disabled";
1303		};
1304
1305		qspi: spi@58003000 {
1306			compatible = "st,stm32f469-qspi";
1307			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1308			reg-names = "qspi", "qspi_mm";
1309			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1310			dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1311			       <&mdma1 22 0x10 0x100008 0x0 0x0>;
1312			dma-names = "tx", "rx";
1313			clocks = <&rcc QSPI_K>;
1314			resets = <&rcc QSPI_R>;
1315			status = "disabled";
1316		};
1317
1318		sdmmc1: sdmmc@58005000 {
1319			compatible = "arm,pl18x", "arm,primecell";
1320			arm,primecell-periphid = <0x10153180>;
1321			reg = <0x58005000 0x1000>;
1322			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1323			interrupt-names = "cmd_irq";
1324			clocks = <&rcc SDMMC1_K>;
1325			clock-names = "apb_pclk";
1326			resets = <&rcc SDMMC1_R>;
1327			cap-sd-highspeed;
1328			cap-mmc-highspeed;
1329			max-frequency = <120000000>;
1330			status = "disabled";
1331		};
1332
1333		sdmmc2: sdmmc@58007000 {
1334			compatible = "arm,pl18x", "arm,primecell";
1335			arm,primecell-periphid = <0x10153180>;
1336			reg = <0x58007000 0x1000>;
1337			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1338			interrupt-names = "cmd_irq";
1339			clocks = <&rcc SDMMC2_K>;
1340			clock-names = "apb_pclk";
1341			resets = <&rcc SDMMC2_R>;
1342			cap-sd-highspeed;
1343			cap-mmc-highspeed;
1344			max-frequency = <120000000>;
1345			status = "disabled";
1346		};
1347
1348		crc1: crc@58009000 {
1349			compatible = "st,stm32f7-crc";
1350			reg = <0x58009000 0x400>;
1351			clocks = <&rcc CRC1>;
1352			status = "disabled";
1353		};
1354
1355		stmmac_axi_config_0: stmmac-axi-config {
1356			snps,wr_osr_lmt = <0x7>;
1357			snps,rd_osr_lmt = <0x7>;
1358			snps,blen = <0 0 0 0 16 8 4>;
1359		};
1360
1361		ethernet0: ethernet@5800a000 {
1362			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1363			reg = <0x5800a000 0x2000>;
1364			reg-names = "stmmaceth";
1365			interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1366			interrupt-names = "macirq";
1367			clock-names = "stmmaceth",
1368				      "mac-clk-tx",
1369				      "mac-clk-rx",
1370				      "ethstp";
1371			clocks = <&rcc ETHMAC>,
1372				 <&rcc ETHTX>,
1373				 <&rcc ETHRX>,
1374				 <&rcc ETHSTP>;
1375			st,syscon = <&syscfg 0x4>;
1376			snps,mixed-burst;
1377			snps,pbl = <2>;
1378			snps,en-tx-lpi-clockgating;
1379			snps,axi-config = <&stmmac_axi_config_0>;
1380			snps,tso;
1381			status = "disabled";
1382		};
1383
1384		usbh_ohci: usbh-ohci@5800c000 {
1385			compatible = "generic-ohci";
1386			reg = <0x5800c000 0x1000>;
1387			clocks = <&rcc USBH>;
1388			resets = <&rcc USBH_R>;
1389			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1390			status = "disabled";
1391		};
1392
1393		usbh_ehci: usbh-ehci@5800d000 {
1394			compatible = "generic-ehci";
1395			reg = <0x5800d000 0x1000>;
1396			clocks = <&rcc USBH>;
1397			resets = <&rcc USBH_R>;
1398			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1399			companion = <&usbh_ohci>;
1400			status = "disabled";
1401		};
1402
1403		ltdc: display-controller@5a001000 {
1404			compatible = "st,stm32-ltdc";
1405			reg = <0x5a001000 0x400>;
1406			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1407				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1408			clocks = <&rcc LTDC_PX>;
1409			clock-names = "lcd";
1410			resets = <&rcc LTDC_R>;
1411			status = "disabled";
1412		};
1413
1414		iwdg2: watchdog@5a002000 {
1415			compatible = "st,stm32mp1-iwdg";
1416			reg = <0x5a002000 0x400>;
1417			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1418			clock-names = "pclk", "lsi";
1419			status = "disabled";
1420		};
1421
1422		usbphyc: usbphyc@5a006000 {
1423			#address-cells = <1>;
1424			#size-cells = <0>;
1425			compatible = "st,stm32mp1-usbphyc";
1426			reg = <0x5a006000 0x1000>;
1427			clocks = <&rcc USBPHY_K>;
1428			resets = <&rcc USBPHY_R>;
1429			status = "disabled";
1430
1431			usbphyc_port0: usb-phy@0 {
1432				#phy-cells = <0>;
1433				reg = <0>;
1434			};
1435
1436			usbphyc_port1: usb-phy@1 {
1437				#phy-cells = <1>;
1438				reg = <1>;
1439			};
1440		};
1441
1442		usart1: serial@5c000000 {
1443			compatible = "st,stm32h7-uart";
1444			reg = <0x5c000000 0x400>;
1445			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1446			clocks = <&rcc USART1_K>;
1447			resets = <&rcc USART1_R>;
1448			status = "disabled";
1449		};
1450
1451		spi6: spi@5c001000 {
1452			#address-cells = <1>;
1453			#size-cells = <0>;
1454			compatible = "st,stm32h7-spi";
1455			reg = <0x5c001000 0x400>;
1456			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1457			clocks = <&rcc SPI6_K>;
1458			resets = <&rcc SPI6_R>;
1459			dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1460			       <&mdma1 35 0x0 0x40002 0x0 0x0>;
1461			dma-names = "rx", "tx";
1462			status = "disabled";
1463		};
1464
1465		i2c4: i2c@5c002000 {
1466			compatible = "st,stm32f7-i2c";
1467			reg = <0x5c002000 0x400>;
1468			interrupt-names = "event", "error";
1469			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1470				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1471			clocks = <&rcc I2C4_K>;
1472			resets = <&rcc I2C4_R>;
1473			#address-cells = <1>;
1474			#size-cells = <0>;
1475		};
1476
1477		rtc: rtc@5c004000 {
1478			compatible = "st,stm32mp1-rtc";
1479			reg = <0x5c004000 0x400>;
1480			clocks = <&rcc RTCAPB>, <&rcc RTC>;
1481			clock-names = "pclk", "rtc_ck";
1482			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1483			status = "disabled";
1484		};
1485
1486		bsec: efuse@5c005000 {
1487			compatible = "st,stm32mp15-bsec";
1488			reg = <0x5c005000 0x400>;
1489			#address-cells = <1>;
1490			#size-cells = <1>;
1491			ts_cal1: calib@5c {
1492				reg = <0x5c 0x2>;
1493			};
1494			ts_cal2: calib@5e {
1495				reg = <0x5e 0x2>;
1496			};
1497			mac_addr: mac_addr@e4 {
1498				reg = <0xe4 0x8>;
1499				st,non-secure-otp;
1500			};
1501		};
1502
1503		etzpc: etzpc@5c007000 {
1504			compatible = "st,stm32-etzpc";
1505			reg = <0x5C007000 0x400>;
1506			clocks = <&rcc TZPC>;
1507			status = "disabled";
1508			secure-status = "okay";
1509		};
1510
1511		i2c6: i2c@5c009000 {
1512			compatible = "st,stm32f7-i2c";
1513			reg = <0x5c009000 0x400>;
1514			interrupt-names = "event", "error";
1515			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1516				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1517			clocks = <&rcc I2C6_K>;
1518			resets = <&rcc I2C6_R>;
1519			#address-cells = <1>;
1520			#size-cells = <0>;
1521			status = "disabled";
1522		};
1523
1524		/*
1525		 * Break node order to solve dependency probe issue between
1526		 * pinctrl and exti.
1527		 */
1528		pinctrl: pin-controller@50002000 {
1529			#address-cells = <1>;
1530			#size-cells = <1>;
1531			compatible = "st,stm32mp157-pinctrl";
1532			ranges = <0 0x50002000 0xa400>;
1533			interrupt-parent = <&exti>;
1534			st,syscfg = <&exti 0x60 0xff>;
1535			pins-are-numbered;
1536
1537			gpioa: gpio@50002000 {
1538				gpio-controller;
1539				#gpio-cells = <2>;
1540				interrupt-controller;
1541				#interrupt-cells = <2>;
1542				reg = <0x0 0x400>;
1543				clocks = <&rcc GPIOA>;
1544				st,bank-name = "GPIOA";
1545				status = "disabled";
1546			};
1547
1548			gpiob: gpio@50003000 {
1549				gpio-controller;
1550				#gpio-cells = <2>;
1551				interrupt-controller;
1552				#interrupt-cells = <2>;
1553				reg = <0x1000 0x400>;
1554				clocks = <&rcc GPIOB>;
1555				st,bank-name = "GPIOB";
1556				status = "disabled";
1557			};
1558
1559			gpioc: gpio@50004000 {
1560				gpio-controller;
1561				#gpio-cells = <2>;
1562				interrupt-controller;
1563				#interrupt-cells = <2>;
1564				reg = <0x2000 0x400>;
1565				clocks = <&rcc GPIOC>;
1566				st,bank-name = "GPIOC";
1567				status = "disabled";
1568			};
1569
1570			gpiod: gpio@50005000 {
1571				gpio-controller;
1572				#gpio-cells = <2>;
1573				interrupt-controller;
1574				#interrupt-cells = <2>;
1575				reg = <0x3000 0x400>;
1576				clocks = <&rcc GPIOD>;
1577				st,bank-name = "GPIOD";
1578				status = "disabled";
1579			};
1580
1581			gpioe: gpio@50006000 {
1582				gpio-controller;
1583				#gpio-cells = <2>;
1584				interrupt-controller;
1585				#interrupt-cells = <2>;
1586				reg = <0x4000 0x400>;
1587				clocks = <&rcc GPIOE>;
1588				st,bank-name = "GPIOE";
1589				status = "disabled";
1590			};
1591
1592			gpiof: gpio@50007000 {
1593				gpio-controller;
1594				#gpio-cells = <2>;
1595				interrupt-controller;
1596				#interrupt-cells = <2>;
1597				reg = <0x5000 0x400>;
1598				clocks = <&rcc GPIOF>;
1599				st,bank-name = "GPIOF";
1600				status = "disabled";
1601			};
1602
1603			gpiog: gpio@50008000 {
1604				gpio-controller;
1605				#gpio-cells = <2>;
1606				interrupt-controller;
1607				#interrupt-cells = <2>;
1608				reg = <0x6000 0x400>;
1609				clocks = <&rcc GPIOG>;
1610				st,bank-name = "GPIOG";
1611				status = "disabled";
1612			};
1613
1614			gpioh: gpio@50009000 {
1615				gpio-controller;
1616				#gpio-cells = <2>;
1617				interrupt-controller;
1618				#interrupt-cells = <2>;
1619				reg = <0x7000 0x400>;
1620				clocks = <&rcc GPIOH>;
1621				st,bank-name = "GPIOH";
1622				status = "disabled";
1623			};
1624
1625			gpioi: gpio@5000a000 {
1626				gpio-controller;
1627				#gpio-cells = <2>;
1628				interrupt-controller;
1629				#interrupt-cells = <2>;
1630				reg = <0x8000 0x400>;
1631				clocks = <&rcc GPIOI>;
1632				st,bank-name = "GPIOI";
1633				status = "disabled";
1634			};
1635
1636			gpioj: gpio@5000b000 {
1637				gpio-controller;
1638				#gpio-cells = <2>;
1639				interrupt-controller;
1640				#interrupt-cells = <2>;
1641				reg = <0x9000 0x400>;
1642				clocks = <&rcc GPIOJ>;
1643				st,bank-name = "GPIOJ";
1644				status = "disabled";
1645			};
1646
1647			gpiok: gpio@5000c000 {
1648				gpio-controller;
1649				#gpio-cells = <2>;
1650				interrupt-controller;
1651				#interrupt-cells = <2>;
1652				reg = <0xa000 0x400>;
1653				clocks = <&rcc GPIOK>;
1654				st,bank-name = "GPIOK";
1655				status = "disabled";
1656			};
1657		};
1658
1659		pinctrl_z: pin-controller-z@54004000 {
1660			#address-cells = <1>;
1661			#size-cells = <1>;
1662			compatible = "st,stm32mp157-z-pinctrl";
1663			ranges = <0 0x54004000 0x400>;
1664			pins-are-numbered;
1665			interrupt-parent = <&exti>;
1666			st,syscfg = <&exti 0x60 0xff>;
1667
1668			gpioz: gpio@54004000 {
1669				gpio-controller;
1670				#gpio-cells = <2>;
1671				interrupt-controller;
1672				#interrupt-cells = <2>;
1673				reg = <0 0x400>;
1674				clocks = <&rcc GPIOZ>;
1675				st,bank-name = "GPIOZ";
1676				st,bank-ioport = <11>;
1677				status = "disabled";
1678			};
1679		};
1680	};
1681
1682	mlahb: ahb {
1683		compatible = "st,mlahb", "simple-bus";
1684		#address-cells = <1>;
1685		#size-cells = <1>;
1686		ranges;
1687		dma-ranges = <0x00000000 0x38000000 0x10000>,
1688			     <0x10000000 0x10000000 0x60000>,
1689			     <0x30000000 0x30000000 0x60000>;
1690
1691		m4_rproc: m4@10000000 {
1692			compatible = "st,stm32mp1-m4";
1693			reg = <0x10000000 0x40000>,
1694			      <0x30000000 0x40000>,
1695			      <0x38000000 0x10000>;
1696			resets = <&rcc MCU_R>;
1697			st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1698			st,syscfg-tz = <&rcc 0x000 0x1>;
1699			status = "disabled";
1700		};
1701	};
1702};
1703