1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (c) 2017, Linaro Limited
4  */
5 
6 #ifndef __KERNEL_CACHE_HELPERS_H
7 #define __KERNEL_CACHE_HELPERS_H
8 
9 #ifndef __ASSEMBLER__
10 #include <arm.h>
11 #include <types_ext.h>
12 #endif
13 
14 /* Data Cache set/way op type defines */
15 #define DCACHE_OP_INV		0x0
16 #define DCACHE_OP_CLEAN_INV	0x1
17 #define DCACHE_OP_CLEAN		0x2
18 
19 #ifndef __ASSEMBLER__
20 void dcache_cleaninv_range(void *addr, size_t size);
21 void dcache_clean_range(void *addr, size_t size);
22 void dcache_inv_range(void *addr, size_t size);
23 void dcache_clean_range_pou(void *addr, size_t size);
24 
25 void icache_inv_all(void);
26 void icache_inv_range(void *addr, size_t size);
27 void icache_inv_user_range(void *addr, size_t size);
28 
29 void dcache_op_louis(unsigned long op_type);
30 void dcache_op_all(unsigned long op_type);
31 
32 void dcache_op_level1(unsigned long op_type);
33 void dcache_op_level2(unsigned long op_type);
34 void dcache_op_level3(unsigned long op_type);
35 
36 /*
37  * Get system cache line size from ARM system configuration registers.
38  */
dcache_get_line_size(void)39 static inline unsigned int dcache_get_line_size(void)
40 {
41 	uint32_t value = read_ctr();
42 
43 	return CTR_WORD_SIZE <<
44 		((value >> CTR_DMINLINE_SHIFT) & CTR_DMINLINE_MASK);
45 }
46 #endif /*!__ASSEMBLER__*/
47 
48 #endif /*__KERNEL_CACHE_HELPERS_H*/
49