1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright 2019 Broadcom.
4 */
5
6 #include <bcm_elog.h>
7 #include <console.h>
8 #include <drivers/gic.h>
9 #include <drivers/serial8250_uart.h>
10 #include <kernel/boot.h>
11 #include <kernel/interrupt.h>
12 #include <kernel/panic.h>
13 #include <mm/core_memprot.h>
14 #include <mm/tee_pager.h>
15 #include <platform_config.h>
16 #include <stdint.h>
17
18 static struct gic_data gic_data;
19 struct serial8250_uart_data console_data;
20
21 #ifdef BCM_DEVICE0_BASE
22 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE0_BASE, BCM_DEVICE0_SIZE);
23 #endif
24 #ifdef BCM_DEVICE1_BASE
25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE1_BASE, BCM_DEVICE1_SIZE);
26 #endif
27 #ifdef BCM_DEVICE2_BASE
28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE2_BASE, BCM_DEVICE2_SIZE);
29 #endif
30 #ifdef BCM_DEVICE3_BASE
31 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE3_BASE, BCM_DEVICE3_SIZE);
32 #endif
33 #ifdef BCM_DEVICE4_BASE
34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE4_BASE, BCM_DEVICE4_SIZE);
35 #endif
36 #ifdef BCM_DEVICE5_BASE
37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, BCM_DEVICE5_BASE, BCM_DEVICE5_SIZE);
38 #endif
39 #ifdef BCM_DRAM0_NS_BASE
40 register_dynamic_shm(BCM_DRAM0_NS_BASE, BCM_DRAM0_NS_SIZE);
41 #endif
42 #ifdef BCM_DRAM1_NS_BASE
43 register_dynamic_shm(BCM_DRAM1_NS_BASE, BCM_DRAM1_NS_SIZE);
44 #endif
45 #ifdef BCM_DRAM2_NS_BASE
46 register_dynamic_shm(BCM_DRAM2_NS_BASE, BCM_DRAM2_NS_SIZE);
47 #endif
48 #ifdef BCM_DRAM0_SEC_BASE
49 register_phys_mem(MEM_AREA_RAM_SEC, BCM_DRAM0_SEC_BASE, BCM_DRAM0_SEC_SIZE);
50 #endif
51 #ifdef CFG_BCM_ELOG_AP_UART_LOG_BASE
52 register_phys_mem(MEM_AREA_IO_NSEC, CFG_BCM_ELOG_AP_UART_LOG_BASE,
53 CFG_BCM_ELOG_AP_UART_LOG_SIZE);
54 #endif
55 #ifdef CFG_BCM_ELOG_BASE
56 register_phys_mem(MEM_AREA_RAM_NSEC, CFG_BCM_ELOG_BASE, CFG_BCM_ELOG_SIZE);
57 #endif
58
plat_trace_ext_puts(const char * str)59 void plat_trace_ext_puts(const char *str)
60 {
61 const char *p;
62
63 for (p = str; *p; p++)
64 bcm_elog_putchar(*p);
65 }
66
console_init(void)67 void console_init(void)
68 {
69 serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
70 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
71 register_serial_console(&console_data.chip);
72
73 bcm_elog_init(CFG_BCM_ELOG_AP_UART_LOG_BASE,
74 CFG_BCM_ELOG_AP_UART_LOG_SIZE);
75 }
76
itr_core_handler(void)77 void itr_core_handler(void)
78 {
79 gic_it_handle(&gic_data);
80 }
81
main_init_gic(void)82 void main_init_gic(void)
83 {
84 vaddr_t gicd_base;
85
86 gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC, 1);
87
88 if (!gicd_base)
89 panic();
90
91 gic_init_base_addr(&gic_data, 0, gicd_base);
92 itr_init(&gic_data.chip);
93
94 }
95