1/* SPDX-License-Identifier: BSD-2-Clause */
2/*
3 * Copyright (c) 2014, STMicroelectronics International N.V.
4 * Copyright (c) 2016, Wind River Systems.
5 * All rights reserved.
6 * Copyright 2019 NXP
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 *
14 * 2. Redistributions in binary form must reproduce the above copyright notice,
15 * this list of conditions and the following disclaimer in the documentation
16 * and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/*
32 * Entry points for the A9 inits, A9 revision specific or not.
33 * It is assume no stack is available when these routines are called.
34 * It is assume each routine is called with return address in LR
35 * and with ARM registers R0, R1, R2, R3 being scratchable.
36 */
37
38#include <arm32.h>
39#include <arm32_macros.S>
40#include <arm32_macros_cortex_a9.S>
41#include <asm.S>
42#include <kernel/tz_ssvce_def.h>
43#include <platform_config.h>
44
45.section .text
46.balign 4
47.code 32
48
49/*
50 * Cortex A9 early configuration
51 *
52 * Use registers R0-R3.
53 * No stack usage.
54 * LR store return address.
55 * Trap CPU in case of error.
56 */
57FUNC plat_cpu_reset_early , :
58	/*
59	 * Under very rare timing circumstances, transition into streaming
60	 * mode might create a data corruption
61	 * Configurations affected
62	 * This erratum affects configurations with either:
63	 * - One processor if the ACP is present
64	 * - Two or more processors
65	 * This erratum can be worked round by setting bit[22] of the
66	 * undocumented Diagnostic Control Register to 1. This
67	 * register is encoded as CP15 c15 0 c0 1.
68	 * The bit can be written in Secure state only, with the following
69	 * Read/Modify/Write code sequence:
70	 * MRC p15,0,rt,c15,c0,1
71	 * ORR rt,rt,#0x00400000
72	 * MCR p15,0,rt,c15,c0,1
73	 * When this bit is set, the processor is unable to switch into
74	 * Read-Allocate (streaming) mode, which means this erratum cannot
75	 * occur. Setting this bit could possibly result in a visible drop
76	 * in performance for routines that perform intensive memory
77	 * accesses, such as memset() or memcpy(). However, the workaround
78	 * is not expected to create any significant performance degradation
79	 * in most standard applications.
80	 */
81#if defined(CFG_MX6QP) || defined(CFG_MX6Q) || defined(CFG_MX6D) || \
82	 defined(CFG_MX6DL)
83	read_diag r0
84	orr r0, r0, #1 << 22
85	write_diag r0
86#endif
87	/*
88	 * Disallow NSec to mask FIQ [bit4: FW=0]
89	 * Allow NSec to manage Imprecise Abort [bit5: AW=1]
90	 * Imprecise Abort trapped to Abort Mode [bit3: EA=0]
91	 * In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0]
92	 * IRQ always trapped to IRQ Mode [bit1: IRQ=0]
93	 * Secure World [bit0: NS=0]
94	 */
95	mov r0, #SCR_AW
96	write_scr r0
97
98	/*
99	 * Mandated HW config loaded
100	 *
101	 * SCTLR = 0x00004000
102	 * - Round-Robin replac. for icache, btac, i/duTLB (bit14: RoundRobin)
103	 *
104	 * ACTRL = 0x000000[46(i.MX6SLL),47]
105	 * - core always in full SMP (FW bit0=[0(i.MX6SLL),1], SMP bit6=1)
106	 * - L2 write full line of zero disabled (bit3=0)
107	 *   (keep WFLZ low. Will be set once outer L2 is ready)
108	 * - L1 Prefetch enable (bit2=1)
109	 * - L2 Prefetch hint enable (bit1=1)
110	 *
111	 * NSACR = 0x00020C00
112	 * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0)
113	 * - Nsec can lockdown TLB (TL bit17=1)
114	 * - NSec cannot access PLE (PLE bit16=0)
115	 * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11)
116	 *
117	 * PCR
118	 * - no change latency, enable clk gating
119	 */
120	mov_imm r0, 0x00004000
121	write_sctlr r0
122
123#ifdef CFG_MX6SLL
124	mov_imm r0, 0x00000046
125#else
126	mov_imm r0, 0x00000047
127#endif
128	write_actlr r0
129
130	mov_imm r0, 0x00020C00
131	write_nsacr r0
132
133	read_pcr r0
134	orr r0, r0, #0x1
135	write_pcr r0
136
137	mov pc, lr
138END_FUNC plat_cpu_reset_early
139