1# 2# Define the cryptographic algorithm to be built 3# 4 5# 6# CAAM Debug: define 3x32 bits value (same bit used to debug a module) 7# CFG_DBG_CAAM_TRACE Module print trace 8# CFG_DBG_CAAM_DESC Module descriptor dump 9# CFG_DBG_CAAM_BUF Module buffer dump 10# 11# DBG_HAL BIT32(0) // HAL trace 12# DBG_CTRL BIT32(1) // Controller trace 13# DBG_MEM BIT32(2) // Memory utility trace 14# DBG_SGT BIT32(3) // Scatter Gather trace 15# DBG_PWR BIT32(4) // Power trace 16# DBG_JR BIT32(5) // Job Ring trace 17# DBG_RNG BIT32(6) // RNG trace 18# DBG_HASH BIT32(7) // Hash trace 19# DBG_RSA BIT32(8) // RSA trace 20# DBG_CIPHER BIT32(9) // Cipher trace 21# DBG_BLOB BIT32(10) // BLOB trace 22# DBG_DMAOBJ BIT32(11) // DMA Object Trace 23# DBG_ECC BIT32(12) // ECC trace 24# DBG_DH BIT32(13) // DH Trace 25# DBG_DSA BIT32(14) // DSA trace 26CFG_DBG_CAAM_TRACE ?= 0x2 27CFG_DBG_CAAM_DESC ?= 0x0 28CFG_DBG_CAAM_BUF ?= 0x0 29 30# Enable the BLOB module used for the hardware unique key 31CFG_NXP_CAAM_BLOB_DRV ?= y 32 33# Value to round up to when allocating SGT entries 34CFG_CAAM_SGT_ALIGN ?= 1 35 36# Version of the SGT implementation to use 37CFG_NXP_CAAM_SGT_V1 ?= y 38 39ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX)),y) 40$(call force, CFG_CAAM_SIZE_ALIGN,4) 41$(call force, CFG_JR_BLOCK_SIZE,0x10000) 42$(call force,CFG_JR_INDEX,3) 43$(call force,CFG_JR_INT,486) 44else ifneq (,$(filter y, $(CFG_MX8MM) $(CFG_MX8MN) $(CFG_MX8MP) $(CFG_MX8MQ))) 45$(call force,CFG_CAAM_SIZE_ALIGN,1) 46$(call force,CFG_JR_BLOCK_SIZE,0x1000) 47$(call force,CFG_JR_INDEX,2) 48$(call force,CFG_JR_INT,146) 49else ifneq (,$(filter y, $(CFG_MX8ULP))) 50$(call force,CFG_CAAM_SIZE_ALIGN,1) 51$(call force,CFG_JR_BLOCK_SIZE,0x1000) 52$(call force,CFG_JR_INDEX,2) 53$(call force,CFG_JR_INT,114) 54$(call force,CFG_CAAM_NO_ITR,y) 55else 56$(call force, CFG_CAAM_SIZE_ALIGN,1) 57$(call force, CFG_JR_BLOCK_SIZE,0x1000) 58$(call force, CFG_JR_INDEX,0) 59$(call force, CFG_JR_INT,137) 60endif 61 62# 63# Configuration of the Crypto Driver 64# 65ifeq ($(CFG_CRYPTO_DRIVER), y) 66 67# Crypto Driver Debug 68# DRV_DBG_TRACE BIT32(0) // Driver trace 69# DRV_DBG_BUF BIT32(1) // Driver dump Buffer 70CFG_CRYPTO_DRIVER_DEBUG ?= 0 71 72$(call force, CFG_NXP_CAAM_RUNTIME_JR, y) 73 74# 75# Definition of all HW accelerations for all i.MX 76# 77$(call force, CFG_NXP_CAAM_RNG_DRV, y) 78$(call force, CFG_WITH_SOFTWARE_PRNG,n) 79 80# Force to 'y' the CFG_NXP_CAAM_xxx_DRV to enable the CAAM HW driver 81# and enable the associated CFG_CRYPTO_DRV_xxx Crypto driver 82# API 83# 84# Example: Enable CFG_CRYPTO_DRV_HASH and CFG_NXP_CAAM_HASH_DRV 85# $(eval $(call cryphw-enable-drv-hw, HASH)) 86define cryphw-enable-drv-hw 87_var := $(strip $(1)) 88$$(call force, CFG_NXP_CAAM_$$(_var)_DRV, y) 89$$(call force, CFG_CRYPTO_DRV_$$(_var), y) 90endef 91 92# Return 'y' if at least one of the variable 93# CFG_CRYPTO_xxx_HW is 'y' 94cryphw-one-enabled = $(call cfg-one-enabled, \ 95 $(foreach v,$(1), CFG_NXP_CAAM_$(v)_DRV)) 96 97# Definition of the HW and Cryto Driver Algorithm supported by all i.MX 98$(eval $(call cryphw-enable-drv-hw, HASH)) 99$(eval $(call cryphw-enable-drv-hw, CIPHER)) 100$(eval $(call cryphw-enable-drv-hw, HMAC)) 101$(eval $(call cryphw-enable-drv-hw, CMAC)) 102 103ifneq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) \ 104 $(CFG_MX6S) $(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX) $(CFG_MX7ULP) $(CFG_MX8ULP)), y) 105$(eval $(call cryphw-enable-drv-hw, RSA)) 106$(eval $(call cryphw-enable-drv-hw, ECC)) 107$(eval $(call cryphw-enable-drv-hw, DH)) 108$(eval $(call cryphw-enable-drv-hw, DSA)) 109 110# Define the RSA Private Key Format used by the CAAM 111# Format #1: (n, d) 112# Format #2: (p, q, d) 113# Format #3: (p, q, dp, dq, qp) 114CFG_NXP_CAAM_RSA_KEY_FORMAT ?= 3 115 116endif 117 118$(call force, CFG_NXP_CAAM_ACIPHER_DRV, $(call cryphw-one-enabled, RSA ECC DH DSA)) 119$(call force, CFG_CRYPTO_DRV_MAC, $(call cryphw-one-enabled, HMAC CMAC)) 120 121# 122# Enable Cryptographic Driver interface 123# 124CFG_CRYPTO_DRV_ACIPHER ?= $(CFG_NXP_CAAM_ACIPHER_DRV) 125endif 126