1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright 2021 NXP 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef PLATFORM_CONFIG_H 31 #define PLATFORM_CONFIG_H 32 33 #include <mm/generic_ram_layout.h> 34 35 #define STACK_ALIGNMENT 64 36 37 /* console uart define */ 38 #define CONSOLE_UART_BASE UART0_BASE 39 40 /* Platform specific defines */ 41 #if defined(PLATFORM_FLAVOR_ls1021aqds) || defined(PLATFORM_FLAVOR_ls1021atwr) 42 /* DUART 1 */ 43 #define UART0_BASE 0x021C0500 44 #define DCFG_BASE 0x01EE0000 45 #define DCFG_CCSR_BRR 0xE4 46 #define DCFG_SCRATCHRW1 0x200 47 48 #define CSU_BASE 0x01510000 49 #define CSU_CSL_START 0x0 50 #define CSU_CSL_END 0xE8 51 #define CSU_CSL30 0x78 52 #define CSU_CSL37 0x94 53 54 /* Central Security Unit register values */ 55 #define CSU_ACCESS_ALL 0x00FF00FF 56 #define CSU_ACCESS_SEC_ONLY 0x003F003F 57 #define CSU_SETTING_LOCK 0x01000100 58 59 #define GIC_BASE 0x01400000 60 #define GICC_OFFSET 0x2000 61 #define GICD_OFFSET 0x1000 62 #define CAAM_BASE 0x01700000 63 #endif 64 65 #if defined(PLATFORM_FLAVOR_ls1012ardb) || defined(PLATFORM_FLAVOR_ls1012afrwy) 66 /* DUART 1 */ 67 #define UART0_BASE 0x021C0500 68 #define GIC_BASE 0x01400000 69 #define GICC_OFFSET 0x2000 70 #define GICD_OFFSET 0x1000 71 #define CAAM_BASE 0x01700000 72 #endif 73 74 #if defined(PLATFORM_FLAVOR_ls1043ardb) || defined(PLATFORM_FLAVOR_ls1046ardb) 75 /* DUART 1 */ 76 #define UART0_BASE 0x021C0500 77 #define GIC_BASE 0x01400000 78 #define GICC_OFFSET 0x20000 79 #define GICD_OFFSET 0x10000 80 #define CAAM_BASE 0x01700000 81 #endif 82 83 #if defined(PLATFORM_FLAVOR_ls1088ardb) 84 /* DUART 1 */ 85 #define UART0_BASE 0x021C0500 86 #define GIC_BASE 0x06000000 87 #define GICC_OFFSET 0x0 88 #define GICD_OFFSET 0x0 89 #define CAAM_BASE 0x08000000 90 #endif 91 92 #if defined(PLATFORM_FLAVOR_ls2088ardb) 93 /* DUART 1 */ 94 #define UART0_BASE 0x021C0600 95 #define GIC_BASE 0x06000000 96 #define GICC_OFFSET 0x0 97 #define GICD_OFFSET 0x0 98 #define CAAM_BASE 0x08000000 99 #endif 100 101 #if defined(PLATFORM_FLAVOR_ls1028ardb) 102 /* DUART 1 */ 103 #define UART0_BASE 0x021C0500 104 #define GIC_BASE 0x06000000 105 #define GICC_OFFSET 0x0 106 #define GICD_OFFSET 0x0 107 #define CAAM_BASE 0x08000000 108 #endif 109 110 #if defined(PLATFORM_FLAVOR_lx2160ardb) 111 /* DUART 1 */ 112 #define UART0_BASE 0x021C0000 113 #define GIC_BASE 0x06000000 114 #define GICC_OFFSET 0x0 115 #define GICD_OFFSET 0x0 116 #define CAAM_BASE 0x08000000 117 #endif 118 119 #if defined(PLATFORM_FLAVOR_lx2160aqds) 120 /* DUART 1 */ 121 #define UART0_BASE 0x021C0000 122 #define GIC_BASE 0x06000000 123 #define GICC_OFFSET 0x0 124 #define GICD_OFFSET 0x0 125 #define CAAM_BASE 0x08000000 126 #endif 127 128 #endif /*PLATFORM_CONFIG_H*/ 129