1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (C) 2017 Timesys Corporation.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
11 *
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <io.h>
30 #include <kernel/boot.h>
31 #include <kernel/tz_ssvce_pl310.h>
32 #include <mm/core_memprot.h>
33 #include <mm/core_mmu.h>
34 #include <sama5d2.h>
35 #include <sam_sfr.h>
36 #include <types_ext.h>
37
38 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
39
pl310_base(void)40 vaddr_t pl310_base(void)
41 {
42 static void *va;
43
44 if (cpu_mmu_enabled()) {
45 if (!va)
46 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1);
47 return (vaddr_t)va;
48 }
49 return PL310_BASE;
50 }
51
arm_cl2_config(vaddr_t pl310_base)52 void arm_cl2_config(vaddr_t pl310_base)
53 {
54 io_write32(pl310_base + PL310_CTRL, 0);
55 io_write32(sam_sfr_base() + AT91_SFR_L2CC_HRAMC, 0x1);
56 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT);
57 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT);
58 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT);
59
60 /* invalidate all cache ways */
61 arm_cl2_invbyway(pl310_base);
62 }
63
arm_cl2_enable(vaddr_t pl310_base)64 void arm_cl2_enable(vaddr_t pl310_base)
65 {
66 /* Enable PL310 ctrl -> only set lsb bit */
67 io_write32(pl310_base + PL310_CTRL, 1);
68 }
69