1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2014-2016, Linaro Limited 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <util.h> 10 #include <mm/generic_ram_layout.h> 11 12 /* Below are platform/SoC settings specific to stm platform flavors */ 13 14 #if defined(PLATFORM_FLAVOR_b2260) 15 16 #define CPU_IOMEM_BASE 0x08760000 17 #define CPU_IOMEM_SIZE 0x000a0000 18 #define CPU_PORT_FILT_START 0x40000000 19 #define CPU_PORT_FILT_END 0xC0000000 20 #define STXHXXX_LPM_PERIPH_BASE 0x09700000 21 #define RNG_BASE 0x08A89000 22 #define RNG_SIZE 0x00001000 23 24 #define ASC_NUM 21 25 #define UART_CONSOLE_BASE ST_ASC21_REGS_BASE 26 27 #elif defined(PLATFORM_FLAVOR_cannes) 28 29 #define CPU_IOMEM_BASE 0x08760000 30 #define CPU_IOMEM_SIZE 0x000a0000 31 #define CPU_PORT_FILT_START 0x40000000 32 #define CPU_PORT_FILT_END 0xC0000000 33 #define STXHXXX_LPM_PERIPH_BASE 0x09400000 34 #define RNG_BASE 0x08A89000 35 #define RNG_SIZE 0x00001000 36 37 #define ASC_NUM 20 38 #define UART_CONSOLE_BASE ST_ASC20_REGS_BASE 39 40 #else /* defined(PLATFORM_FLAVOR_xxx) */ 41 42 #error "Unknown platform flavor" 43 44 #endif /* defined(PLATFORM_FLAVOR_xxx) */ 45 46 #define PL310_BASE (CPU_IOMEM_BASE + 0x2000) 47 #define GIC_DIST_BASE (CPU_IOMEM_BASE + 0x1000) 48 #define SCU_BASE (CPU_IOMEM_BASE + 0x0000) 49 #define GIC_CPU_BASE (CPU_IOMEM_BASE + 0x0100) 50 #define ST_ASC20_REGS_BASE (STXHXXX_LPM_PERIPH_BASE + 0x00130000) 51 #define ST_ASC21_REGS_BASE (STXHXXX_LPM_PERIPH_BASE + 0x00131000) 52 53 /* Below are settings common to stm platform flavors */ 54 55 /* Make stacks aligned to data cache line length */ 56 #define STACK_ALIGNMENT 32 57 58 /* 59 * CP15 Secure ConTroL Register (SCTLR 60 * 61 * - Round-Robin replac. for icache, btac, i/duTLB (bit14: RoundRobin) 62 */ 63 #define CPU_SCTLR_INIT 0x00004000 64 65 /* 66 * CP15 Auxiliary ConTroL Register (ACTRL) 67 * 68 * - core always in full SMP (FW bit0=1, SMP bit6=1) 69 * - L2 write full line of zero disabled (bit3=0) 70 * (keep WFLZ low. Will be set once outer L2 is ready) 71 */ 72 #define CPU_ACTLR_INIT 0x00000041 73 74 /* 75 * CP15 NonSecure Access Control Register (NSACR) 76 * 77 * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) 78 * - Nsec can lockdown TLB (TL bit17=1) 79 * - NSec cannot access PLE (PLE bit16=0) 80 * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11) 81 */ 82 #define CPU_NSACR_INIT 0x00020C00 83 84 /* 85 * CP15 Power Control Register (PCR) 86 * 87 * - no change latency, enable clk gating 88 */ 89 #define CPU_PCR_INIT 0x00000001 90 91 92 /* 93 * SCU Secure Access Control / NonSecure Access Control 94 * 95 * SAC: Both secure CPU access SCU (bit[3:0]). 96 * NSAC: Both nonsec cpu access SCU (bit[3:0]), private timers (bit[7:4]) 97 * and global timers (bit[11:8]). 98 */ 99 #if !defined(SCU_SAC_INIT) || !defined(SCU_NSAC_INIT) 100 #define SCU_CPUS_MASK (SHIFT_U32(1, CFG_TEE_CORE_NB_CORE) - 1) 101 102 #define SCU_SAC_INIT SCU_CPUS_MASK 103 #define SCU_NSAC_INIT (SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_SCU_SHIFT) | \ 104 SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_PTIMER_SHIFT) | \ 105 SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_GTIMER_SHIFT)) 106 #endif 107 108 /* 109 * PL310 TAG RAM Control Register 110 * 111 * bit[10:8]:1 - 2 cycle of write accesses latency 112 * bit[6:4]:1 - 2 cycle of read accesses latency 113 * bit[2:0]:1 - 2 cycle of setup latency 114 */ 115 #ifndef PL310_TAG_RAM_CTRL_INIT 116 #define PL310_TAG_RAM_CTRL_INIT 0x00000111 117 #endif 118 119 /* 120 * PL310 DATA RAM Control Register 121 * 122 * bit[10:8]:2 - 3 cycle of write accesses latency 123 * bit[6:4]:2 - 3 cycle of read accesses latency 124 * bit[2:0]:2 - 3 cycle of setup latency 125 */ 126 #ifndef PL310_DATA_RAM_CTRL_INIT 127 #define PL310_DATA_RAM_CTRL_INIT 0x00000222 128 #endif 129 130 /* 131 * PL310 Auxiliary Control Register 132 * 133 * I/Dcache prefetch enabled (bit29:28=2b11) 134 * NS can access interrupts (bit27=1) 135 * NS can lockown cache lines (bit26=1) 136 * Pseudo-random replacement policy (bit25=0) 137 * Force write allocated (default) 138 * Shared attribute internally ignored (bit22=1, bit13=0) 139 * Parity disabled (bit21=0) 140 * Event monitor disabled (bit20=0) 141 * Platform fmavor specific way config: 142 * - way size (bit19:17) 143 * - way associciativity (bit16) 144 * Store buffer device limitation enabled (bit11=1) 145 * Cacheable accesses have high prio (bit10=0) 146 * Full Line Zero (FLZ) disabled (bit0=0) 147 */ 148 #ifndef PL310_AUX_CTRL_INIT 149 #define PL310_AUX_CTRL_INIT 0x3C480800 150 #endif 151 152 /* 153 * PL310 Prefetch Control Register 154 * 155 * Double linefill disabled (bit30=0) 156 * I/D prefetch enabled (bit29:28=2b11) 157 * Prefetch drop enabled (bit24=1) 158 * Incr double linefill disable (bit23=0) 159 * Prefetch offset = 7 (bit4:0) 160 */ 161 #define PL310_PREFETCH_CTRL_INIT 0x31000007 162 163 /* 164 * PL310 Power Register 165 * 166 * Dynamic clock gating enabled 167 * Standby mode enabled 168 */ 169 #define PL310_POWER_CTRL_INIT 0x00000003 170 171 /* 172 * SCU Control Register : CTRL = 0x00000065 173 * - ic stanby enable=1 174 * - scu standby enable=1 175 * - scu enable=1 176 */ 177 #define SCU_CTRL_INIT 0x00000065 178 179 /* 180 * Register non-secure DDR chunks for dynamic shared memory: these are 181 * DDR ranges that do not include OP-TEE secure memory. 182 * Some Stm platforms may reserve beginning of the DDR for non REE memory. 183 */ 184 185 #ifdef CFG_DDR_START 186 /* Carvout out secure RAM range (emulated SRAM is expected near DRAM) */ 187 #if defined(CFG_WITH_PAGER) && defined(TZSRAM_BASE) 188 #if TZSRAM_BASE >= CFG_DDR_START 189 #define STM_SECDDR_BASE MIN_UNSAFE(TZSRAM_BASE, TZDRAM_BASE) 190 #define STM_SECDDR_END MAX_UNSAFE(TZSRAM_BASE + TZSRAM_SIZE, \ 191 TZDRAM_BASE + TZDRAM_SIZE) 192 #endif /*TZSRAM_BASE >= CFG_DDR_START*/ 193 #endif /*CFG_WITH_PAGER && TZSRAM_BASE*/ 194 195 #ifndef STM_SECDDR_BASE 196 #define STM_SECDDR_BASE TZDRAM_BASE 197 #define STM_SECDDR_END (TZDRAM_BASE + TZDRAM_SIZE) 198 #endif 199 200 #define STM_SECDDR_SIZE (STM_SECDDR_END - STM_SECDDR_BASE) 201 /* Register the DDR chunks that do not intersect the secure DDR single area */ 202 #define DRAM0_BASE (CFG_DDR_START + CFG_STM_RSV_DRAM_STARTBYTES) 203 #define DRAM0_SIZE (STM_SECDDR_BASE - DRAM0_BASE) 204 #if (STM_SECDDR_END < 0x80000000ULL) 205 #define DRAM1_BASE STM_SECDDR_END 206 #define DRAM1_SIZE ((CFG_DDR_START - DRAM1_BASE) + CFG_DDR_SIZE) 207 #endif 208 #endif /*CFG_DDR_START*/ 209 210 #endif /* PLATFORM_CONFIG_H */ 211