1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2015, Linaro Limited
4 * Copyright (c) 2017, Socionext Inc.
5 */
6
7 #include <console.h>
8 #include <drivers/gic.h>
9 #include <drivers/serial8250_uart.h>
10 #include <io.h>
11 #include <kernel/boot.h>
12 #include <kernel/panic.h>
13 #include <mm/tee_pager.h>
14 #include <platform_config.h>
15 #include <stdint.h>
16
17 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
18 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
19 CORE_MMU_PGDIR_SIZE);
20
21 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
22 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
23 CORE_MMU_PGDIR_SIZE);
24
25 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
26 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
27 CORE_MMU_PGDIR_SIZE);
28
29 #ifdef DRAM0_BASE
30 register_ddr(DRAM0_BASE, DRAM0_SIZE);
31 #endif
32 #ifdef DRAM1_BASE
33 register_ddr(DRAM1_BASE, DRAM1_SIZE);
34 #endif
35
36 static struct gic_data gic_data;
37
38 static struct serial8250_uart_data console_data;
39
main_init_gic(void)40 void main_init_gic(void)
41 {
42 vaddr_t gicc_base, gicd_base;
43
44 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
45 MEM_AREA_IO_SEC, CORE_MMU_PGDIR_SIZE);
46 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
47 MEM_AREA_IO_SEC, CORE_MMU_PGDIR_SIZE);
48
49 gic_init_base_addr(&gic_data, gicc_base, gicd_base);
50 itr_init(&gic_data.chip);
51 }
52
itr_core_handler(void)53 void itr_core_handler(void)
54 {
55 gic_it_handle(&gic_data);
56 }
57
console_init(void)58 void console_init(void)
59 {
60 /* Init UART */
61 serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
62 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
63
64 /* Register console */
65 register_serial_console(&console_data.chip);
66 }
67