1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2016-2020, Linaro Limited
4 * Copyright (c) 2014, STMicroelectronics International N.V.
5 */
6
7 #include <arm.h>
8 #include <console.h>
9 #include <drivers/gic.h>
10 #include <drivers/pl011.h>
11 #include <drivers/tzc400.h>
12 #include <initcall.h>
13 #include <keep.h>
14 #include <kernel/boot.h>
15 #include <kernel/interrupt.h>
16 #include <kernel/misc.h>
17 #include <kernel/notif.h>
18 #include <kernel/panic.h>
19 #include <kernel/spinlock.h>
20 #include <kernel/tee_time.h>
21 #include <mm/core_memprot.h>
22 #include <mm/core_mmu.h>
23 #include <platform_config.h>
24 #include <sm/psci.h>
25 #include <stdint.h>
26 #include <string.h>
27 #include <trace.h>
28
29 static struct gic_data gic_data __nex_bss;
30 static struct pl011_data console_data __nex_bss;
31
32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
33 #if defined(PLATFORM_FLAVOR_fvp)
34 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE);
35 #endif
36 #if defined(PLATFORM_FLAVOR_qemu_virt)
37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE);
38 #endif
39 #ifdef DRAM0_BASE
40 register_ddr(DRAM0_BASE, DRAM0_SIZE);
41 #endif
42 #ifdef DRAM1_BASE
43 register_ddr(DRAM1_BASE, DRAM1_SIZE);
44 #endif
45
46 #ifdef GIC_BASE
47
48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
50
main_init_gic(void)51 void main_init_gic(void)
52 {
53 vaddr_t gicc_base;
54 vaddr_t gicd_base;
55
56 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
57 MEM_AREA_IO_SEC, GIC_CPU_REG_SIZE);
58 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
59 MEM_AREA_IO_SEC, GIC_DIST_REG_SIZE);
60 if (!gicc_base || !gicd_base)
61 panic();
62
63 #if defined(CFG_WITH_ARM_TRUSTED_FW)
64 /* On ARMv8, GIC configuration is initialized in ARM-TF */
65 gic_init_base_addr(&gic_data, gicc_base, gicd_base);
66 #else
67 /* Initialize GIC */
68 gic_init(&gic_data, gicc_base, gicd_base);
69 #endif
70 itr_init(&gic_data.chip);
71 }
72
73 #if !defined(CFG_WITH_ARM_TRUSTED_FW)
main_secondary_init_gic(void)74 void main_secondary_init_gic(void)
75 {
76 gic_cpu_init(&gic_data);
77 }
78 #endif
79
80 #endif
81
itr_core_handler(void)82 void itr_core_handler(void)
83 {
84 gic_it_handle(&gic_data);
85 }
86
console_init(void)87 void console_init(void)
88 {
89 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
90 CONSOLE_BAUDRATE);
91 register_serial_console(&console_data.chip);
92 }
93
94 #if defined(IT_CONSOLE_UART) && \
95 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV3))
96 /*
97 * This cannot be enabled with TF-A and GICv3 because TF-A then need to
98 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently
99 * there's no way of TF-A to know which interrupts that OP-TEE will serve.
100 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it
101 * will hang in EL3 since the interrupt will just be delivered again and
102 * again.
103 */
104
read_console(void)105 static void read_console(void)
106 {
107 struct serial_chip *cons = &console_data.chip;
108
109 while (cons->ops->have_rx_data(cons)) {
110 int ch __maybe_unused = cons->ops->getchar(cons);
111
112 DMSG("got 0x%x", ch);
113 }
114 }
115
console_itr_cb(struct itr_handler * h __maybe_unused)116 static enum itr_return console_itr_cb(struct itr_handler *h __maybe_unused)
117 {
118 if (notif_async_is_started()) {
119 /*
120 * Asynchronous notifications are enabled, lets read from
121 * uart in the bottom half instead.
122 */
123 itr_disable(IT_CONSOLE_UART);
124 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF);
125 } else {
126 read_console();
127 }
128 return ITRR_HANDLED;
129 }
130
131 static struct itr_handler console_itr = {
132 .it = IT_CONSOLE_UART,
133 .flags = ITRF_TRIGGER_LEVEL,
134 .handler = console_itr_cb,
135 };
136 DECLARE_KEEP_PAGER(console_itr);
137
atomic_console_notif(struct notif_driver * ndrv __unused,enum notif_event ev __maybe_unused)138 static void atomic_console_notif(struct notif_driver *ndrv __unused,
139 enum notif_event ev __maybe_unused)
140 {
141 DMSG("Asynchronous notifications started, event %d", (int)ev);
142 }
143 DECLARE_KEEP_PAGER(atomic_console_notif);
144
yielding_console_notif(struct notif_driver * ndrv __unused,enum notif_event ev)145 static void yielding_console_notif(struct notif_driver *ndrv __unused,
146 enum notif_event ev)
147 {
148 switch (ev) {
149 case NOTIF_EVENT_DO_BOTTOM_HALF:
150 read_console();
151 itr_enable(IT_CONSOLE_UART);
152 break;
153 case NOTIF_EVENT_STOPPED:
154 DMSG("Asynchronous notifications stopped");
155 itr_enable(IT_CONSOLE_UART);
156 break;
157 default:
158 EMSG("Unknown event %d", (int)ev);
159 }
160 }
161
162 struct notif_driver console_notif = {
163 .atomic_cb = atomic_console_notif,
164 .yielding_cb = yielding_console_notif,
165 };
166
init_console_itr(void)167 static TEE_Result init_console_itr(void)
168 {
169 itr_add(&console_itr);
170 itr_enable(IT_CONSOLE_UART);
171 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF))
172 notif_register_driver(&console_notif);
173 return TEE_SUCCESS;
174 }
175 driver_init(init_console_itr);
176 #endif
177
178 #ifdef CFG_TZC400
179 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE);
180
init_tzc400(void)181 static TEE_Result init_tzc400(void)
182 {
183 void *va;
184
185 DMSG("Initializing TZC400");
186
187 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE);
188 if (!va) {
189 EMSG("TZC400 not mapped");
190 panic();
191 }
192
193 tzc_init((vaddr_t)va);
194 tzc_dump_state();
195
196 return TEE_SUCCESS;
197 }
198
199 service_init(init_tzc400);
200 #endif /*CFG_TZC400*/
201
202 #if defined(PLATFORM_FLAVOR_qemu_virt)
release_secondary_early_hpen(size_t pos)203 static void release_secondary_early_hpen(size_t pos)
204 {
205 struct mailbox {
206 uint64_t ep;
207 uint64_t hpen[];
208 } *mailbox;
209
210 if (cpu_mmu_enabled())
211 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC,
212 SECRAM_COHERENT_SIZE);
213 else
214 mailbox = (void *)SECRAM_BASE;
215
216 if (!mailbox)
217 panic();
218
219 mailbox->ep = TEE_LOAD_ADDR;
220 dsb_ishst();
221 mailbox->hpen[pos] = 1;
222 dsb_ishst();
223 sev();
224 }
225
psci_cpu_on(uint32_t core_id,uint32_t entry,uint32_t context_id)226 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id)
227 {
228 size_t pos = get_core_pos_mpidr(core_id);
229 static bool core_is_released[CFG_TEE_CORE_NB_CORE];
230
231 if (!pos || pos >= CFG_TEE_CORE_NB_CORE)
232 return PSCI_RET_INVALID_PARAMETERS;
233
234 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry);
235
236 if (core_is_released[pos]) {
237 EMSG("core %zu already released", pos);
238 return PSCI_RET_DENIED;
239 }
240 core_is_released[pos] = true;
241
242 boot_set_core_ns_entry(pos, entry, context_id);
243 release_secondary_early_hpen(pos);
244
245 return PSCI_RET_SUCCESS;
246 }
247 #endif /*PLATFORM_FLAVOR_qemu_virt*/
248