1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2014, Linaro Limited 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 #include <stdint.h> 11 12 /* Make stacks aligned to data cache line length */ 13 #define STACK_ALIGNMENT 64 14 15 #if defined(PLATFORM_FLAVOR_fvp) 16 17 #define GIC_BASE 0x2c000000 18 #define UART0_BASE 0x1c090000 19 #define UART1_BASE 0x1c0a0000 20 #define UART2_BASE 0x1c0b0000 21 #define UART3_BASE 0x1c0c0000 22 #define TZC400_BASE 0x2a4a0000 23 24 #define IT_UART1 38 25 26 #define CONSOLE_UART_BASE UART1_BASE 27 #define IT_CONSOLE_UART IT_UART1 28 29 #elif defined(PLATFORM_FLAVOR_juno) 30 31 #define GIC_BASE 0x2c010000 32 33 /* FPGA UART0 */ 34 #define UART0_BASE 0x1c090000 35 /* FPGA UART1 */ 36 #define UART1_BASE 0x1c0a0000 37 /* SoC UART0 */ 38 #define UART2_BASE 0x7ff80000 39 /* SoC UART1 */ 40 #define UART3_BASE 0x7ff70000 41 42 43 #define UART0_CLK_IN_HZ 24000000 44 #define UART1_CLK_IN_HZ 24000000 45 #define UART2_CLK_IN_HZ 7273800 46 #define UART3_CLK_IN_HZ 7273800 47 48 49 #define IT_UART3 116 50 51 #define CONSOLE_UART_BASE UART3_BASE 52 #define IT_CONSOLE_UART IT_UART3 53 #define CONSOLE_UART_CLK_IN_HZ UART3_CLK_IN_HZ 54 55 #elif defined(PLATFORM_FLAVOR_qemu_virt) 56 57 #define GIC_BASE 0x08000000 58 #define UART0_BASE 0x09000000 59 #define UART1_BASE 0x09040000 60 #define PCSC_BASE 0x09100000 61 62 #define IT_UART1 40 63 #define IT_PCSC 37 64 65 #define CONSOLE_UART_BASE UART1_BASE 66 #define IT_CONSOLE_UART IT_UART1 67 68 #elif defined(PLATFORM_FLAVOR_qemu_armv8a) 69 70 #define GIC_BASE 0x08000000 71 #define UART0_BASE 0x09000000 72 #define UART1_BASE 0x09040000 73 74 #define IT_UART1 40 75 76 #define CONSOLE_UART_BASE UART1_BASE 77 #define IT_CONSOLE_UART IT_UART1 78 79 #else 80 #error "Unknown platform flavor" 81 #endif 82 83 #if defined(PLATFORM_FLAVOR_fvp) 84 /* 85 * FVP specifics. 86 */ 87 88 #define DRAM0_BASE 0x80000000 89 #define DRAM0_SIZE 0x7f000000 90 91 #define DRAM1_BASE 0x880000000UL 92 #define DRAM1_SIZE 0x180000000UL 93 94 #define TZCDRAM_BASE 0xff000000 95 #define TZCDRAM_SIZE 0x01000000 96 97 #define GICC_OFFSET 0x0 98 #define GICD_OFFSET 0x3000000 99 100 #elif defined(PLATFORM_FLAVOR_juno) 101 /* 102 * Juno specifics. 103 */ 104 105 #define DRAM0_BASE 0x80000000 106 #define DRAM0_SIZE 0x7F000000 107 108 #define DRAM1_BASE 0x880000000UL 109 #define DRAM1_SIZE 0x180000000UL 110 111 #define GICC_OFFSET 0x1f000 112 #define GICD_OFFSET 0 113 114 #elif defined(PLATFORM_FLAVOR_qemu_virt) 115 /* 116 * QEMU virt specifics. 117 */ 118 119 #define SECRAM_BASE 0x0e000000 120 #define SECRAM_COHERENT_SIZE 4096 121 122 #define GICD_OFFSET 0 123 #define GICC_OFFSET 0x10000 124 125 #elif defined(PLATFORM_FLAVOR_qemu_armv8a) 126 127 #define GICD_OFFSET 0 128 #define GICC_OFFSET 0x10000 129 130 #else 131 #error "Unknown platform flavor" 132 #endif 133 134 #ifdef GIC_BASE 135 #define GICD_BASE (GIC_BASE + GICD_OFFSET) 136 #define GICC_BASE (GIC_BASE + GICC_OFFSET) 137 #endif 138 139 #ifndef UART_BAUDRATE 140 #define UART_BAUDRATE 115200 141 #endif 142 #ifndef CONSOLE_BAUDRATE 143 #define CONSOLE_BAUDRATE UART_BAUDRATE 144 #endif 145 146 /* For virtual platforms where there isn't a clock */ 147 #ifndef CONSOLE_UART_CLK_IN_HZ 148 #define CONSOLE_UART_CLK_IN_HZ 1 149 #endif 150 151 #endif /*PLATFORM_CONFIG_H*/ 152