1PLATFORM_FLAVOR ?= zcu102
2
3include core/arch/arm/cpu/cortex-armv8-0.mk
4
5$(call force,CFG_TEE_CORE_NB_CORE,4)
6$(call force,CFG_CDNS_UART,y)
7$(call force,CFG_GIC,y)
8$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
9$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
10
11# Disable core ASLR for two reasons:
12# 1. There is no source for ALSR seed, as ATF does not provide a
13#    DTB to OP-TEE. Hardware RNG is also not currently supported.
14# 2. OP-TEE does not boot with enabled CFG_CORE_ASLR.
15$(call force,CFG_CORE_ASLR,n)
16
17ifeq ($(CFG_ARM64_core),y)
18$(call force,CFG_WITH_LPAE,y)
19
20# ZynqMP supports up to 40 bits of physical addresses
21CFG_CORE_ARM64_PA_BITS ?= 40
22else
23$(call force,CFG_ARM32_core,y)
24endif
25
26ifneq (,$(filter $(PLATFORM_FLAVOR),zcu102 zc1751_dc1 zc1751_dc2))
27# ZCU102 features 4 GiB of DDR
28ifeq ($(CFG_ARM64_core),y)
29CFG_DDR_SIZE ?= 0x100000000
30else
31# On 32 bit build limit to 2 GiB of RAM
32CFG_DDR_SIZE ?= 0x80000000
33endif
34endif
35
36ifneq (,$(filter $(PLATFORM_FLAVOR),ultra96))
37# Ultra96 features 2 GiB of DDR
38CFG_DDR_SIZE ?= 0x80000000
39endif
40
41# By default use DT address as specified by Xilinx
42CFG_DT_ADDR ?= 0x100000
43
44CFG_TZDRAM_START ?= 0x60000000
45CFG_TZDRAM_SIZE  ?= 0x10000000
46CFG_SHMEM_START  ?= 0x70000000
47CFG_SHMEM_SIZE   ?= 0x10000000
48
49CFG_WITH_STATS ?= y
50CFG_CRYPTO_WITH_CE ?= y
51
52CFG_ZYNQMP_PM ?= $(CFG_ARM64_core)
53
54ifeq ($(CFG_RPMB_FS),y)
55$(call force,CFG_ZYNQMP_HUK,y,Mandated by CFG_RPMB_FS)
56endif
57
58ifeq ($(CFG_ZYNQMP_HUK),y)
59$(call force,CFG_ZYNQMP_CSU_AES,y,Mandated by CFG_ZYNQMP_HUK)
60$(call force,CFG_ZYNQMP_CSU_PUF,y,Mandated by CFG_ZYNQMP_HUK)
61endif
62
63ifeq ($(CFG_ZYNQMP_CSU_AES),y)
64$(call force,CFG_ZYNQMP_CSUDMA,y,Mandated by CFG_ZYNQMP_CSU_AES)
65$(call force,CFG_DT,y,Mandated by CFG_ZYNQMP_CSU_AES)
66endif
67
68ifneq (,$(filter y, $(CFG_ZYNQMP_CSU_PUF) $(CFG_ZYNQMP_CSUDMA) $(CFG_ZYNQMP_CSU_AES)))
69$(call force,CFG_ZYNQMP_CSU,y,Mandated by CFG_ZYNQMP_CSU* clients)
70endif
71