1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 * 5 * Brief Control Registers. 6 */ 7 #ifndef __CTRL_REGS_H__ 8 #define __CTRL_REGS_H__ 9 10 #include <util.h> 11 12 /* Master Configuration */ 13 #define MCFGR 0x0004 14 #define MCFGR_WDE BIT32(30) 15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) 16 #define BM_MCFGR_AXIPIPE SHIFT_U32(0xF, 4) 17 18 /* Job Ring x MID */ 19 #define JRxMIDR_SIZE 0x8 20 #define JR0MIDR_MS 0x0010 21 #define JR0MIDR_LS 0x0014 22 #define JRxMIDR_MS(idx) (JR0MIDR_MS + (idx) * JRxMIDR_SIZE) 23 #define JRxMIDR_LS(idx) (JR0MIDR_LS + (idx) * JRxMIDR_SIZE) 24 25 #define JRxMIDR_MS_LMID BIT32(31) 26 #define JRxMIDR_MS_LAMTD BIT32(17) 27 #define JRxMIDR_MS_AMTD BIT32(16) 28 #if !defined(CFG_MX7ULP) 29 #define JRxMIDR_MS_JROWN_NS BIT32(3) 30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) 31 32 #define JRxMIDR_LS_NONSEQ_NS BIT32(19) 33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) 34 #define JRxMIDR_LS_SEQ_NS BIT32(3) 35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) 36 #else 37 #define JRxMIDR_MS_JROWN_NS BIT32(4) 38 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0xF, 0) 39 40 #define JRxMIDR_LS_NONSEQ_NS BIT32(20) 41 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0xF, 16) 42 #define JRxMIDR_LS_SEQ_NS BIT32(4) 43 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0xF, 0) 44 #endif 45 46 /* Security Configuration */ 47 #define SCFGR 0x000C 48 #define BS_SCFGR_MPCURVE 28 49 #define BM_SCFGR_MPCURVE SHIFT_U32(0xF, BS_SCFGR_MPCURVE) 50 #define BM_SCFGR_MPMRL BIT32(26) 51 52 /* Manufacturing Protection Message */ 53 #define MPMR 0x0380 54 #define MPMR_NB_REG 0x20 55 56 #endif /* __CTRL_REGS_H__ */ 57