1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2019, 2021 NXP 4 * 5 * Brief Control Registers. 6 */ 7 #ifndef __CTRL_REGS_H__ 8 #define __CTRL_REGS_H__ 9 10 #include <util.h> 11 12 /* Master Configuration */ 13 #define MCFGR 0x0004 14 #define MCFGR_WDE BIT32(30) 15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) 16 #define BM_MCFGR_AXIPIPE SHIFT_U32(0xF, 4) 17 18 /* Job Ring x MID */ 19 #define JRxMIDR_SIZE 0x8 20 #define JR0MIDR_MS 0x0010 21 #define JR0MIDR_LS 0x0014 22 #define JRxMIDR_MS(idx) (JR0MIDR_MS + (idx) * JRxMIDR_SIZE) 23 #define JRxMIDR_LS(idx) (JR0MIDR_LS + (idx) * JRxMIDR_SIZE) 24 25 #define JRxMIDR_MS_LMID BIT32(31) 26 #define JRxMIDR_MS_LAMTD BIT32(17) 27 #define JRxMIDR_MS_TZ BIT32(15) 28 #define JRxMIDR_MS_AMTD BIT32(16) 29 #define JRxMIDR_MS_JROWN_NS BIT32(3) 30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) 31 32 #define JRxMIDR_LS_NONSEQ_NS BIT32(19) 33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) 34 #define JRxMIDR_LS_SEQ_NS BIT32(3) 35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) 36 37 /* Security Configuration */ 38 #define SCFGR 0x000C 39 40 #endif /* __CTRL_REGS_H__ */ 41 42