1# Automatically generated, do not edit 2# Based on register description in 3# ARM Architecture Reference Manual 4# ARMv7-A and ARMv7-R edition 5# Issue C.c 6 7# B3.18.1 Identification registers, functional group 8 9 # IMPLEMENTATION DEFINED Auxiliary ID Register 10 .macro read_aidr reg 11 mrc p15, 1, \reg, c0, c0, 7 12 .endm 13 14 # Cache Size ID Registers 15 .macro read_ccsidr reg 16 mrc p15, 1, \reg, c0, c0, 0 17 .endm 18 19 # Cache Level ID Register 20 .macro read_clidr reg 21 mrc p15, 1, \reg, c0, c0, 1 22 .endm 23 24 # Cache Size Selection Register 25 .macro read_csselr reg 26 mrc p15, 2, \reg, c0, c0, 0 27 .endm 28 29 # Cache Size Selection Register 30 .macro write_csselr reg 31 mcr p15, 2, \reg, c0, c0, 0 32 .endm 33 34 # Cache Type Register 35 .macro read_ctr reg 36 mrc p15, 0, \reg, c0, c0, 1 37 .endm 38 39 # Auxiliary Feature Register 0 40 .macro read_id_afr0 reg 41 mrc p15, 0, \reg, c0, c1, 3 42 .endm 43 44 # Debug Feature Register 0 45 .macro read_id_dfr0 reg 46 mrc p15, 0, \reg, c0, c1, 2 47 .endm 48 49 # Instruction Set Attribute Register 0 50 .macro read_id_isar0 reg 51 mrc p15, 0, \reg, c0, c2, 0 52 .endm 53 54 # Instruction Set Attribute Register 1 55 .macro read_id_isar1 reg 56 mrc p15, 0, \reg, c0, c2, 1 57 .endm 58 59 # Instruction Set Attribute Register 2 60 .macro read_id_isar2 reg 61 mrc p15, 0, \reg, c0, c2, 2 62 .endm 63 64 # Instruction Set Attribute Register 3 65 .macro read_id_isar3 reg 66 mrc p15, 0, \reg, c0, c2, 3 67 .endm 68 69 # Instruction Set Attribute Register 4 70 .macro read_id_isar4 reg 71 mrc p15, 0, \reg, c0, c2, 4 72 .endm 73 74 # Instruction Set Attribute Register 5 75 .macro read_id_isar5 reg 76 mrc p15, 0, \reg, c0, c2, 5 77 .endm 78 79 # Memory Model Feature Register 0 80 .macro read_id_mmfr0 reg 81 mrc p15, 0, \reg, c0, c1, 4 82 .endm 83 84 # Memory Model Feature Register 1 85 .macro read_id_mmfr1 reg 86 mrc p15, 0, \reg, c0, c1, 5 87 .endm 88 89 # Memory Model Feature Register 2 90 .macro read_id_mmfr2 reg 91 mrc p15, 0, \reg, c0, c1, 6 92 .endm 93 94 # Memory Model Feature Register 3 95 .macro read_id_mmfr3 reg 96 mrc p15, 0, \reg, c0, c1, 7 97 .endm 98 99 # Processor Feature Register 0 100 .macro read_id_pfr0 reg 101 mrc p15, 0, \reg, c0, c1, 0 102 .endm 103 104 # Processor Feature Register 1 105 .macro read_id_pfr1 reg 106 mrc p15, 0, \reg, c0, c1, 1 107 .endm 108 109 # Main ID Register 110 .macro read_midr reg 111 mrc p15, 0, \reg, c0, c0, 0 112 .endm 113 114 # Multiprocessor Affinity Register 115 .macro read_mpidr reg 116 mrc p15, 0, \reg, c0, c0, 5 117 .endm 118 119 # Revision ID Register 120 .macro read_revidr reg 121 mrc p15, 0, \reg, c0, c0, 6 122 .endm 123 124 # TCM Type Register 125 .macro read_tcmtr reg 126 mrc p15, 0, \reg, c0, c0, 2 127 .endm 128 129 # TLB Type Register 130 .macro read_tlbtr reg 131 mrc p15, 0, \reg, c0, c0, 3 132 .endm 133# B3.18.2 Virtual memory control registers, functional group 134 135 # Auxiliary Memory Attribute Indirection Register 0 136 .macro read_amair0 reg 137 mrc p15, 0, \reg, c10, c3, 0 138 .endm 139 140 # Auxiliary Memory Attribute Indirection Register 0 141 .macro write_amair0 reg 142 mcr p15, 0, \reg, c10, c3, 0 143 .endm 144 145 # Auxiliary Memory Attribute Indirection Register 1 146 .macro read_amair1 reg 147 mrc p15, 0, \reg, c10, c3, 1 148 .endm 149 150 # Auxiliary Memory Attribute Indirection Register 1 151 .macro write_amair1 reg 152 mcr p15, 0, \reg, c10, c3, 1 153 .endm 154 155 # Context ID Register 156 .macro read_contextidr reg 157 mrc p15, 0, \reg, c13, c0, 1 158 .endm 159 160 # Context ID Register 161 .macro write_contextidr reg 162 mcr p15, 0, \reg, c13, c0, 1 163 .endm 164 165 # Domain Access Control Register 166 .macro read_dacr reg 167 mrc p15, 0, \reg, c3, c0, 0 168 .endm 169 170 # Domain Access Control Register 171 .macro write_dacr reg 172 mcr p15, 0, \reg, c3, c0, 0 173 .endm 174 175 # Memory Attribute Indirection Register 0 176 .macro read_mair0 reg 177 mrc p15, 0, \reg, c10, c2, 0 178 .endm 179 180 # Memory Attribute Indirection Register 0 181 .macro write_mair0 reg 182 mcr p15, 0, \reg, c10, c2, 0 183 .endm 184 185 # Memory Attribute Indirection Register 1 186 .macro read_mair1 reg 187 mrc p15, 0, \reg, c10, c2, 1 188 .endm 189 190 # Memory Attribute Indirection Register 1 191 .macro write_mair1 reg 192 mcr p15, 0, \reg, c10, c2, 1 193 .endm 194 195 # Normal Memory Remap Register 196 .macro read_nmrr reg 197 mrc p15, 0, \reg, c10, c2, 1 198 .endm 199 200 # Normal Memory Remap Register 201 .macro write_nmrr reg 202 mcr p15, 0, \reg, c10, c2, 1 203 .endm 204 205 # Primary Region Remap Register 206 .macro read_prrr reg 207 mrc p15, 0, \reg, c10, c2, 0 208 .endm 209 210 # Primary Region Remap Register 211 .macro write_prrr reg 212 mcr p15, 0, \reg, c10, c2, 0 213 .endm 214 215 # System Control Register 216 .macro read_sctlr reg 217 mrc p15, 0, \reg, c1, c0, 0 218 .endm 219 220 # System Control Register 221 .macro write_sctlr reg 222 mcr p15, 0, \reg, c1, c0, 0 223 .endm 224 225 # Translation Table Base Control Register 226 .macro read_ttbcr reg 227 mrc p15, 0, \reg, c2, c0, 2 228 .endm 229 230 # Translation Table Base Control Register 231 .macro write_ttbcr reg 232 mcr p15, 0, \reg, c2, c0, 2 233 .endm 234 235 # Translation Table Base Register 0 236 .macro read_ttbr0 reg 237 mrc p15, 0, \reg, c2, c0, 0 238 .endm 239 240 # Translation Table Base Register 0 241 .macro write_ttbr0 reg 242 mcr p15, 0, \reg, c2, c0, 0 243 .endm 244 245 # Translation Table Base Register 0 246 .macro read_ttbr0_64bit reg0, reg1 247 mrrc p15, 0, \reg0, \reg1, c2 248 .endm 249 250 # Translation Table Base Register 0 251 .macro write_ttbr0_64bit reg0, reg1 252 mcrr p15, 0, \reg0, \reg1, c2 253 .endm 254 255 # Translation Table Base Register 1 256 .macro read_ttbr1 reg 257 mrc p15, 0, \reg, c2, c0, 1 258 .endm 259 260 # Translation Table Base Register 1 261 .macro write_ttbr1 reg 262 mcr p15, 0, \reg, c2, c0, 1 263 .endm 264 265 # Translation Table Base Register 1 266 .macro read_ttbr1_64bit reg0, reg1 267 mrrc p15, 1, \reg0, \reg1, c2 268 .endm 269 270 # Translation Table Base Register 1 271 .macro write_ttbr1_64bit reg0, reg1 272 mcrr p15, 1, \reg0, \reg1, c2 273 .endm 274# B3.18.3 PL1 Fault handling registers, functional group 275 276 # Auxiliary Data Fault Status Register 277 .macro read_adfsr reg 278 mrc p15, 0, \reg, c5, c1, 0 279 .endm 280 281 # Auxiliary Data Fault Status Register 282 .macro write_adfsr reg 283 mcr p15, 0, \reg, c5, c1, 0 284 .endm 285 286 # Auxiliary Instruction Fault Status Register 287 .macro read_aifsr reg 288 mrc p15, 0, \reg, c5, c1, 1 289 .endm 290 291 # Auxiliary Instruction Fault Status Register 292 .macro write_aifsr reg 293 mcr p15, 0, \reg, c5, c1, 1 294 .endm 295 296 # Data Fault Address Register 297 .macro read_dfar reg 298 mrc p15, 0, \reg, c6, c0, 0 299 .endm 300 301 # Data Fault Address Register 302 .macro write_dfar reg 303 mcr p15, 0, \reg, c6, c0, 0 304 .endm 305 306 # Data Fault Status Register 307 .macro read_dfsr reg 308 mrc p15, 0, \reg, c5, c0, 0 309 .endm 310 311 # Data Fault Status Register 312 .macro write_dfsr reg 313 mcr p15, 0, \reg, c5, c0, 0 314 .endm 315 316 # Instruction Fault Address Register 317 .macro read_ifar reg 318 mrc p15, 0, \reg, c6, c0, 2 319 .endm 320 321 # Instruction Fault Address Register 322 .macro write_ifar reg 323 mcr p15, 0, \reg, c6, c0, 2 324 .endm 325 326 # Instruction Fault Status Register 327 .macro read_ifsr reg 328 mrc p15, 0, \reg, c5, c0, 1 329 .endm 330 331 # Instruction Fault Status Register 332 .macro write_ifsr reg 333 mcr p15, 0, \reg, c5, c0, 1 334 .endm 335# B3.18.4 Other system control registers, functional group 336 337 # IMPLEMENTATION DEFINED Auxiliary Control Register 338 .macro read_actlr reg 339 mrc p15, 0, \reg, c1, c0, 1 340 .endm 341 342 # IMPLEMENTATION DEFINED Auxiliary Control Register 343 .macro write_actlr reg 344 mcr p15, 0, \reg, c1, c0, 1 345 .endm 346 347 # Coprocessor Access Control Register 348 .macro read_cpacr reg 349 mrc p15, 0, \reg, c1, c0, 2 350 .endm 351 352 # Coprocessor Access Control Register 353 .macro write_cpacr reg 354 mcr p15, 0, \reg, c1, c0, 2 355 .endm 356 357 # FCSE Process ID Register 358 .macro read_fcseidr reg 359 mrc p15, 0, \reg, c13, c0, 0 360 .endm 361 362 # FCSE Process ID Register 363 .macro write_fcseidr reg 364 mcr p15, 0, \reg, c13, c0, 0 365 .endm 366# B3.18.6 Cache maintenance operations, functional group, VMSA 367 368 # Branch predictor invalidate all 369 .macro write_bpiall 370 # Register ignored 371 mcr p15, 0, r0, c7, c5, 6 372 .endm 373 374 # Branch predictor invalidate all IS 375 .macro write_bpiallis 376 # Register ignored 377 mcr p15, 0, r0, c7, c1, 6 378 .endm 379 380 # Branch predictor invalidate by MVA 381 .macro write_bpimva reg 382 mcr p15, 0, \reg, c7, c5, 7 383 .endm 384 385 # Data cache clean and invalidate by MVA PoC 386 .macro write_dccimvac reg 387 mcr p15, 0, \reg, c7, c14, 1 388 .endm 389 390 # Data cache clean and invalidate by set/way 391 .macro write_dccisw reg 392 mcr p15, 0, \reg, c7, c14, 2 393 .endm 394 395 # Data cache clean by MVA PoC 396 .macro write_dccmvac reg 397 mcr p15, 0, \reg, c7, c10, 1 398 .endm 399 400 # Data cache clean by MVA PoU 401 .macro write_dccmvau reg 402 mcr p15, 0, \reg, c7, c11, 1 403 .endm 404 405 # Data cache clean by set/way 406 .macro write_dccsw reg 407 mcr p15, 0, \reg, c7, c10, 2 408 .endm 409 410 # Data cache invalidate by MVA PoC 411 .macro write_dcimvac reg 412 mcr p15, 0, \reg, c7, c6, 1 413 .endm 414 415 # Data cache invalidate by set/way 416 .macro write_dcisw reg 417 mcr p15, 0, \reg, c7, c6, 2 418 .endm 419 420 # Instruction cache invalidate all PoU 421 .macro write_iciallu 422 # Register ignored 423 mcr p15, 0, r0, c7, c5, 0 424 .endm 425 426 # Instruction cache invalidate all PoU, IS 427 .macro write_icialluis 428 # Register ignored 429 mcr p15, 0, r0, c7, c1, 0 430 .endm 431 432 # Instruction cache invalidate by MVA PoU 433 .macro write_icimvau reg 434 mcr p15, 0, \reg, c7, c5, 1 435 .endm 436# B3.18.7 TLB maintenance operations, functional group 437 438 # Invalidate entire unified TLB 439 .macro write_tlbiall 440 # Register ignored 441 mcr p15, 0, r0, c8, c7, 0 442 .endm 443 444 # Invalidate entire unified TLB IS 445 .macro write_tlbiallis 446 # Register ignored 447 mcr p15, 0, r0, c8, c3, 0 448 .endm 449 450 # Invalidate unified TLB by ASID 451 .macro write_tlbiasid reg 452 mcr p15, 0, \reg, c8, c7, 2 453 .endm 454 455 # Invalidate unified TLB by ASID IS 456 .macro write_tlbiasidis reg 457 mcr p15, 0, \reg, c8, c3, 2 458 .endm 459 460 # Invalidate unified TLB by MVA, all ASID 461 .macro write_tlbimvaa reg 462 mcr p15, 0, \reg, c8, c7, 3 463 .endm 464 465 # Invalidate unified TLB by MVA, all ASID IS 466 .macro write_tlbimvaais reg 467 mcr p15, 0, \reg, c8, c3, 3 468 .endm 469 470 # Invalidate unified TLB by MVA 471 .macro write_tlbimva reg 472 mcr p15, 0, \reg, c8, c7, 1 473 .endm 474 475 # Invalidate unified TLB by MVA IS 476 .macro write_tlbimvais reg 477 mcr p15, 0, \reg, c8, c3, 1 478 .endm 479# B3.18.8 Address translation operations, functional group 480 481 # Stages 1 and 2 Non-secure only PL1 read 482 .macro write_ats12nsopr reg 483 mcr p15, 0, \reg, c7, c8, 4 484 .endm 485 486 # Stages 1 and 2 Non-secure only PL1 write 487 .macro write_ats12nsopw reg 488 mcr p15, 0, \reg, c7, c8, 5 489 .endm 490 491 # Stages 1 and 2 Non-secure only unprivileged read 492 .macro write_ats12nsour reg 493 mcr p15, 0, \reg, c7, c8, 6 494 .endm 495 496 # Stages 1 and 2 Non-secure only unprivileged write 497 .macro write_ats12nsouw reg 498 mcr p15, 0, \reg, c7, c8, 7 499 .endm 500 501 # Stage 1 Current state PL1 read 502 .macro write_ats1cpr reg 503 mcr p15, 0, \reg, c7, c8, 0 504 .endm 505 506 # Stage 1 Current state PL1 write 507 .macro write_ats1cpw reg 508 mcr p15, 0, \reg, c7, c8, 1 509 .endm 510 511 # Stage 1 Current state unprivileged read 512 .macro write_ats1cur reg 513 mcr p15, 0, \reg, c7, c8, 2 514 .endm 515 516 # Stage 1 Current state unprivileged write 517 .macro write_ats1cuw reg 518 mcr p15, 0, \reg, c7, c8, 3 519 .endm 520 521 # Stage 1 Hyp mode read 522 .macro write_ats1hr reg 523 mcr p15, 4, \reg, c7, c8, 0 524 .endm 525 526 # Stage 1 Hyp mode write 527 .macro write_ats1hw reg 528 mcr p15, 4, \reg, c7, c8, 1 529 .endm 530 531 # Physical Address Register 532 .macro read_par32 reg 533 mrc p15, 0, \reg, c7, c4, 0 534 .endm 535 536 # Physical Address Register 537 .macro write_par32 reg 538 mcr p15, 0, \reg, c7, c4, 0 539 .endm 540 541 # Physical Address Register 542 .macro read_par64 reg0, reg1 543 mrrc p15, 0, \reg0, \reg1, c7 544 .endm 545 546 # Physical Address Register 547 .macro write_par64 reg0, reg1 548 mcrr p15, 0, \reg0, \reg1, c7 549 .endm 550# B3.18.9 Miscellaneous operations, functional group 551 552 # PL1 only Thread ID Register 553 .macro read_tpidrprw reg 554 mrc p15, 0, \reg, c13, c0, 4 555 .endm 556 557 # PL1 only Thread ID Register 558 .macro write_tpidrprw reg 559 mcr p15, 0, \reg, c13, c0, 4 560 .endm 561 562 # PL0 User Read-Only Thread ID Register 563 .macro read_tpidruro reg 564 mrc p15, 0, \reg, c13, c0, 3 565 .endm 566 567 # PL0 User Read-Only Thread ID Register 568 .macro write_tpidruro reg 569 mcr p15, 0, \reg, c13, c0, 3 570 .endm 571 572 # PL0 User Read/Write Thread ID Register 573 .macro read_tpidrurw reg 574 mrc p15, 0, \reg, c13, c0, 2 575 .endm 576 577 # PL0 User Read/Write Thread ID Register 578 .macro write_tpidrurw reg 579 mcr p15, 0, \reg, c13, c0, 2 580 .endm 581# B3.18.11 Security Extensions registers, functional group 582 583 # Interrupt Status Register 584 .macro read_isr reg 585 mrc p15, 0, \reg, c12, c1, 0 586 .endm 587 588 # Monitor Vector Base Address Register 589 .macro read_mvbar reg 590 mrc p15, 0, \reg, c12, c0, 1 591 .endm 592 593 # Monitor Vector Base Address Register 594 .macro write_mvbar reg 595 mcr p15, 0, \reg, c12, c0, 1 596 .endm 597 598 # Non-Secure Access Control Register 599 .macro read_nsacr reg 600 mrc p15, 0, \reg, c1, c1, 2 601 .endm 602 603 # Non-Secure Access Control Register 604 .macro write_nsacr reg 605 mcr p15, 0, \reg, c1, c1, 2 606 .endm 607 608 # Secure Configuration Register 609 .macro read_scr reg 610 mrc p15, 0, \reg, c1, c1, 0 611 .endm 612 613 # Secure Configuration Register 614 .macro write_scr reg 615 mcr p15, 0, \reg, c1, c1, 0 616 .endm 617 618 # Secure Debug Enable Register 619 .macro read_sder reg 620 mrc p15, 0, \reg, c1, c1, 1 621 .endm 622 623 # Secure Debug Enable Register 624 .macro write_sder reg 625 mcr p15, 0, \reg, c1, c1, 1 626 .endm 627 628 # Vector Base Address Register 629 .macro read_vbar reg 630 mrc p15, 0, \reg, c12, c0, 0 631 .endm 632 633 # Vector Base Address Register 634 .macro write_vbar reg 635 mcr p15, 0, \reg, c12, c0, 0 636 .endm 637# B8.2 Generic Timer registers summary 638 639 # Counter Frequency register 640 .macro read_cntfrq reg 641 mrc p15, 0, \reg, c14, c0, 0 642 .endm 643 644 # Counter Frequency register 645 .macro write_cntfrq reg 646 mcr p15, 0, \reg, c14, c0, 0 647 .endm 648 649 # Physical Count register 650 .macro read_cntpct reg0, reg1 651 mrrc p15, 0, \reg0, \reg1, c14 652 .endm 653 654 # Physical Count register 655 .macro write_cntpct reg0, reg1 656 mcrr p15, 0, \reg0, \reg1, c14 657 .endm 658 659 # Timer PL1 Control register 660 .macro read_cntkctl reg 661 mrc p15, 0, \reg, c14, c1, 0 662 .endm 663 664 # Timer PL1 Control register 665 .macro write_cntkctl reg 666 mcr p15, 0, \reg, c14, c1, 0 667 .endm 668 669 # PL1 Physical TimerValue register 670 .macro read_cntp_tval reg 671 mrc p15, 0, \reg, c14, c2, 0 672 .endm 673 674 # PL1 Physical TimerValue register 675 .macro write_cntp_tval reg 676 mcr p15, 0, \reg, c14, c2, 0 677 .endm 678 679 # PL1 Physical Timer Control register 680 .macro read_cntp_ctl reg 681 mrc p15, 0, \reg, c14, c2, 1 682 .endm 683 684 # PL1 Physical Timer Control register 685 .macro write_cntp_ctl reg 686 mcr p15, 0, \reg, c14, c2, 1 687 .endm 688 689 # Virtual TimerValue register 690 .macro read_cntv_tval reg 691 mrc p15, 0, \reg, c14, c3, 0 692 .endm 693 694 # Virtual TimerValue register 695 .macro write_cntv_tval reg 696 mcr p15, 0, \reg, c14, c3, 0 697 .endm 698 699 # Virtual Timer Control register 700 .macro read_cntv_ctl reg 701 mrc p15, 0, \reg, c14, c3, 1 702 .endm 703 704 # Virtual Timer Control register 705 .macro write_cntv_ctl reg 706 mcr p15, 0, \reg, c14, c3, 1 707 .endm 708 709 # Virtual Count register 710 .macro read_cntvct reg0, reg1 711 mrrc p15, 1, \reg0, \reg1, c14 712 .endm 713 714 # Virtual Count register 715 .macro write_cntvct reg0, reg1 716 mcrr p15, 1, \reg0, \reg1, c14 717 .endm 718 719 # PL1 Physical Timer CompareValue register 720 .macro read_cntp_cval reg0, reg1 721 mrrc p15, 2, \reg0, \reg1, c14 722 .endm 723 724 # PL1 Physical Timer CompareValue register 725 .macro write_cntp_cval reg0, reg1 726 mcrr p15, 2, \reg0, \reg1, c14 727 .endm 728 729 # Virtual Timer CompareValue register 730 .macro read_cntv_cval reg0, reg1 731 mrrc p15, 3, \reg0, \reg1, c14 732 .endm 733 734 # Virtual Timer CompareValue register 735 .macro write_cntv_cval reg0, reg1 736 mcrr p15, 3, \reg0, \reg1, c14 737 .endm 738 739 # Virtual Offset register 740 .macro read_cntvoff reg0, reg1 741 mrrc p15, 4, \reg0, \reg1, c14 742 .endm 743 744 # Virtual Offset register 745 .macro write_cntvoff reg0, reg1 746 mcrr p15, 4, \reg0, \reg1, c14 747 .endm 748# Table C12-7 Performance Monitors register summary 749 750 # Performance Monitors Control Register 751 .macro read_pmcr reg 752 mrc p15, 0, \reg, c9, c12, 0 753 .endm 754 755 # Performance Monitors Control Register 756 .macro write_pmcr reg 757 mcr p15, 0, \reg, c9, c12, 0 758 .endm 759 760 # Performance Monitors Count Enable Set register 761 .macro read_pmcntenset reg 762 mrc p15, 0, \reg, c9, c12, 1 763 .endm 764 765 # Performance Monitors Count Enable Set register 766 .macro write_pmcntenset reg 767 mcr p15, 0, \reg, c9, c12, 1 768 .endm 769 770 # Performance Monitors Count Enable Clear register 771 .macro read_pmcntenclr reg 772 mrc p15, 0, \reg, c9, c12, 2 773 .endm 774 775 # Performance Monitors Count Enable Clear register 776 .macro write_pmcntenclr reg 777 mcr p15, 0, \reg, c9, c12, 2 778 .endm 779 780 # Performance Monitors Overflow Flag Status Register 781 .macro read_pmovsr reg 782 mrc p15, 0, \reg, c9, c12, 3 783 .endm 784 785 # Performance Monitors Overflow Flag Status Register 786 .macro write_pmovsr reg 787 mcr p15, 0, \reg, c9, c12, 3 788 .endm 789 790 # Performance Monitors Software Increment register 791 .macro write_pmswinc reg 792 mcr p15, 0, \reg, c9, c12, 4 793 .endm 794 795 # Performance Monitors Event Counter Selection Register 796 .macro read_pmselr reg 797 mrc p15, 0, \reg, c9, c12, 5 798 .endm 799 800 # Performance Monitors Event Counter Selection Register 801 .macro write_pmselr reg 802 mcr p15, 0, \reg, c9, c12, 5 803 .endm 804 805 # Performance Monitors Common Event Identification reg 0 806 .macro read_pmceid0 reg 807 mrc p15, 0, \reg, c9, c12, 6 808 .endm 809 810 # Performance Monitors Common Event Identification reg 1 811 .macro read_pmceid1 reg 812 mrc p15, 0, \reg, c9, c12, 7 813 .endm 814 815 # Performance Monitors Cycle Count Register 816 .macro read_pmccntr reg 817 mrc p15, 0, \reg, c9, c13, 0 818 .endm 819 820 # Performance Monitors Cycle Count Register 821 .macro write_pmccntr reg 822 mcr p15, 0, \reg, c9, c13, 0 823 .endm 824 825 # Performance Monitors Event Type Select Register 826 .macro read_pmxevtyper reg 827 mrc p15, 0, \reg, c9, c13, 1 828 .endm 829 830 # Performance Monitors Event Type Select Register 831 .macro write_pmxevtyper reg 832 mcr p15, 0, \reg, c9, c13, 1 833 .endm 834 835 # Performance Monitors Event Count Register 836 .macro read_pmxevcntr reg 837 mrc p15, 0, \reg, c9, c13, 2 838 .endm 839 840 # Performance Monitors Event Count Register 841 .macro write_pmxevcntr reg 842 mcr p15, 0, \reg, c9, c13, 2 843 .endm 844 845 # Performance Monitors User Enable Register 846 .macro read_pmuserenr reg 847 mrc p15, 0, \reg, c9, c14, 0 848 .endm 849 850 # Performance Monitors User Enable Register 851 .macro write_pmuserenr reg 852 mcr p15, 0, \reg, c9, c14, 0 853 .endm 854 855 # Performance Monitors Interrupt Enable Set register 856 .macro read_pmintenset reg 857 mrc p15, 0, \reg, c9, c14, 1 858 .endm 859 860 # Performance Monitors Interrupt Enable Set register 861 .macro write_pmintenset reg 862 mcr p15, 0, \reg, c9, c14, 1 863 .endm 864 865 # Performance Monitors Interrupt Enable Clear register 866 .macro read_pmintenclr reg 867 mrc p15, 0, \reg, c9, c14, 2 868 .endm 869 870 # Performance Monitors Interrupt Enable Clear register 871 .macro write_pmintenclr reg 872 mcr p15, 0, \reg, c9, c14, 2 873 .endm 874 875 # Performance Monitors Overflow Flag Status Set register 876 .macro read_pmovsset reg 877 mrc p15, 0, \reg, c9, c14, 3 878 .endm 879 880 # Performance Monitors Overflow Flag Status Set register 881 .macro write_pmovsset reg 882 mcr p15, 0, \reg, c9, c14, 3 883 .endm 884