1 /*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_features.h>
13 #include <arch_helpers.h>
14 #include <bl1/bl1.h>
15 #include <common/bl_common.h>
16 #include <common/debug.h>
17 #include <drivers/auth/auth_mod.h>
18 #include <drivers/console.h>
19 #include <lib/cpus/errata_report.h>
20 #include <lib/utils.h>
21 #include <plat/common/platform.h>
22 #include <smccc_helpers.h>
23 #include <tools_share/uuid.h>
24
25 #include "bl1_private.h"
26
27 static void bl1_load_bl2(void);
28
29 #if ENABLE_PAUTH
30 uint64_t bl1_apiakey[2];
31 #endif
32
33 /*******************************************************************************
34 * Helper utility to calculate the BL2 memory layout taking into consideration
35 * the BL1 RW data assuming that it is at the top of the memory layout.
36 ******************************************************************************/
bl1_calc_bl2_mem_layout(const meminfo_t * bl1_mem_layout,meminfo_t * bl2_mem_layout)37 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
38 meminfo_t *bl2_mem_layout)
39 {
40 assert(bl1_mem_layout != NULL);
41 assert(bl2_mem_layout != NULL);
42
43 /*
44 * Remove BL1 RW data from the scope of memory visible to BL2.
45 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
46 */
47 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
48 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
49 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
50
51 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
52 }
53
54 /*******************************************************************************
55 * Setup function for BL1.
56 ******************************************************************************/
bl1_setup(void)57 void bl1_setup(void)
58 {
59 /* Perform early platform-specific setup */
60 bl1_early_platform_setup();
61
62 /* Perform late platform-specific setup */
63 bl1_plat_arch_setup();
64
65 #if CTX_INCLUDE_PAUTH_REGS
66 /*
67 * Assert that the ARMv8.3-PAuth registers are present or an access
68 * fault will be triggered when they are being saved or restored.
69 */
70 assert(is_armv8_3_pauth_present());
71 #endif /* CTX_INCLUDE_PAUTH_REGS */
72 }
73
74 /*******************************************************************************
75 * Function to perform late architectural and platform specific initialization.
76 * It also queries the platform to load and run next BL image. Only called
77 * by the primary cpu after a cold boot.
78 ******************************************************************************/
bl1_main(void)79 void bl1_main(void)
80 {
81 unsigned int image_id;
82
83 /* Announce our arrival */
84 NOTICE(FIRMWARE_WELCOME_STR);
85 NOTICE("BL1: %s\n", version_string);
86 NOTICE("BL1: %s\n", build_message);
87
88 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
89
90 print_errata_status();
91
92 #if ENABLE_ASSERTIONS
93 u_register_t val;
94 /*
95 * Ensure that MMU/Caches and coherency are turned on
96 */
97 #ifdef __aarch64__
98 val = read_sctlr_el3();
99 #else
100 val = read_sctlr();
101 #endif
102 assert((val & SCTLR_M_BIT) != 0);
103 assert((val & SCTLR_C_BIT) != 0);
104 assert((val & SCTLR_I_BIT) != 0);
105 /*
106 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
107 * provided platform value
108 */
109 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
110 /*
111 * If CWG is zero, then no CWG information is available but we can
112 * at least check the platform value is less than the architectural
113 * maximum.
114 */
115 if (val != 0)
116 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
117 else
118 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
119 #endif /* ENABLE_ASSERTIONS */
120
121 /* Perform remaining generic architectural setup from EL3 */
122 bl1_arch_setup();
123
124 #if TRUSTED_BOARD_BOOT
125 /* Initialize authentication module */
126 auth_mod_init();
127 #endif /* TRUSTED_BOARD_BOOT */
128
129 /* Perform platform setup in BL1. */
130 bl1_platform_setup();
131
132 #if ENABLE_PAUTH
133 /* Store APIAKey_EL1 key */
134 bl1_apiakey[0] = read_apiakeylo_el1();
135 bl1_apiakey[1] = read_apiakeyhi_el1();
136 #endif /* ENABLE_PAUTH */
137
138 /* Get the image id of next image to load and run. */
139 image_id = bl1_plat_get_next_image_id();
140
141 /*
142 * We currently interpret any image id other than
143 * BL2_IMAGE_ID as the start of firmware update.
144 */
145 if (image_id == BL2_IMAGE_ID)
146 bl1_load_bl2();
147 else
148 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
149
150 bl1_prepare_next_image(image_id);
151
152 console_flush();
153 }
154
155 /*******************************************************************************
156 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
157 * Called by the primary cpu after a cold boot.
158 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
159 * loader etc.
160 ******************************************************************************/
bl1_load_bl2(void)161 static void bl1_load_bl2(void)
162 {
163 image_desc_t *desc;
164 image_info_t *info;
165 int err;
166
167 /* Get the image descriptor */
168 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
169 assert(desc != NULL);
170
171 /* Get the image info */
172 info = &desc->image_info;
173 INFO("BL1: Loading BL2\n");
174
175 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
176 if (err != 0) {
177 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
178 plat_error_handler(err);
179 }
180
181 err = load_auth_image(BL2_IMAGE_ID, info);
182 if (err != 0) {
183 ERROR("Failed to load BL2 firmware.\n");
184 plat_error_handler(err);
185 }
186
187 /* Allow platform to handle image information. */
188 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
189 if (err != 0) {
190 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
191 plat_error_handler(err);
192 }
193
194 NOTICE("BL1: Booting BL2\n");
195 }
196
197 /*******************************************************************************
198 * Function called just before handing over to the next BL to inform the user
199 * about the boot progress. In debug mode, also print details about the BL
200 * image's execution context.
201 ******************************************************************************/
bl1_print_next_bl_ep_info(const entry_point_info_t * bl_ep_info)202 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
203 {
204 #ifdef __aarch64__
205 NOTICE("BL1: Booting BL31\n");
206 #else
207 NOTICE("BL1: Booting BL32\n");
208 #endif /* __aarch64__ */
209 print_entry_point_info(bl_ep_info);
210 }
211
212 #if SPIN_ON_BL1_EXIT
print_debug_loop_message(void)213 void print_debug_loop_message(void)
214 {
215 NOTICE("BL1: Debug loop, spinning forever\n");
216 NOTICE("BL1: Please connect the debugger to continue\n");
217 }
218 #endif
219
220 /*******************************************************************************
221 * Top level handler for servicing BL1 SMCs.
222 ******************************************************************************/
bl1_smc_handler(unsigned int smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,unsigned int flags)223 u_register_t bl1_smc_handler(unsigned int smc_fid,
224 u_register_t x1,
225 u_register_t x2,
226 u_register_t x3,
227 u_register_t x4,
228 void *cookie,
229 void *handle,
230 unsigned int flags)
231 {
232 /* BL1 Service UUID */
233 DEFINE_SVC_UUID2(bl1_svc_uid,
234 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75,
235 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
236
237
238 #if TRUSTED_BOARD_BOOT
239 /*
240 * Dispatch FWU calls to FWU SMC handler and return its return
241 * value
242 */
243 if (is_fwu_fid(smc_fid)) {
244 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
245 handle, flags);
246 }
247 #endif
248
249 switch (smc_fid) {
250 case BL1_SMC_CALL_COUNT:
251 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
252
253 case BL1_SMC_UID:
254 SMC_UUID_RET(handle, bl1_svc_uid);
255
256 case BL1_SMC_VERSION:
257 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
258
259 default:
260 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid);
261 SMC_RET1(handle, SMC_UNK);
262 }
263 }
264
265 /*******************************************************************************
266 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
267 * compliance when invoking bl1_smc_handler.
268 ******************************************************************************/
bl1_smc_wrapper(uint32_t smc_fid,void * cookie,void * handle,unsigned int flags)269 u_register_t bl1_smc_wrapper(uint32_t smc_fid,
270 void *cookie,
271 void *handle,
272 unsigned int flags)
273 {
274 u_register_t x1, x2, x3, x4;
275
276 assert(handle != NULL);
277
278 get_smc_params_from_ctx(handle, x1, x2, x3, x4);
279 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
280 }
281