1/*
2 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10
11	.globl	bl2_vector_table
12	.globl	bl2_entrypoint
13
14
15vector_base bl2_vector_table
16	b	bl2_entrypoint
17	b	report_exception	/* Undef */
18	b	report_exception	/* SVC call */
19	b	report_exception	/* Prefetch abort */
20	b	report_exception	/* Data abort */
21	b	report_exception	/* Reserved */
22	b	report_exception	/* IRQ */
23	b	report_exception	/* FIQ */
24
25
26func bl2_entrypoint
27	/*---------------------------------------------
28	 * Save arguments x0 - x3 from BL1 for future
29	 * use.
30	 * ---------------------------------------------
31	 */
32	mov	r9, r0
33	mov	r10, r1
34	mov	r11, r2
35	mov	r12, r3
36
37	/* ---------------------------------------------
38	 * Set the exception vector to something sane.
39	 * ---------------------------------------------
40	 */
41	ldr	r0, =bl2_vector_table
42	stcopr	r0, VBAR
43	isb
44
45	/* --------------------------------------------------------
46	 * Enable the instruction cache - disable speculative loads
47	 * --------------------------------------------------------
48	 */
49	ldcopr	r0, SCTLR
50	orr	r0, r0, #SCTLR_I_BIT
51	bic	r0, r0, #SCTLR_DSSBS_BIT
52	stcopr	r0, SCTLR
53	isb
54
55	/* ---------------------------------------------
56	 * Since BL2 executes after BL1, it is assumed
57	 * here that BL1 has already has done the
58	 * necessary register initializations.
59	 * ---------------------------------------------
60	 */
61
62	/* ---------------------------------------------
63	 * Invalidate the RW memory used by the BL2
64	 * image. This includes the data and NOBITS
65	 * sections. This is done to safeguard against
66	 * possible corruption of this memory by dirty
67	 * cache lines in a system cache as a result of
68	 * use by an earlier boot loader stage.
69	 * ---------------------------------------------
70	 */
71	ldr	r0, =__RW_START__
72	ldr	r1, =__RW_END__
73	sub	r1, r1, r0
74	bl	inv_dcache_range
75
76	/* ---------------------------------------------
77	 * Zero out NOBITS sections. There are 2 of them:
78	 *   - the .bss section;
79	 *   - the coherent memory section.
80	 * ---------------------------------------------
81	 */
82	ldr	r0, =__BSS_START__
83	ldr	r1, =__BSS_END__
84	sub 	r1, r1, r0
85	bl	zeromem
86
87#if USE_COHERENT_MEM
88	ldr	r0, =__COHERENT_RAM_START__
89	ldr	r1, =__COHERENT_RAM_END_UNALIGNED__
90	sub 	r1, r1, r0
91	bl	zeromem
92#endif
93
94	/* --------------------------------------------
95	 * Allocate a stack whose memory will be marked
96	 * as Normal-IS-WBWA when the MMU is enabled.
97	 * There is no risk of reading stale stack
98	 * memory after enabling the MMU as only the
99	 * primary cpu is running at the moment.
100	 * --------------------------------------------
101	 */
102	bl	plat_set_my_stack
103
104	/* ---------------------------------------------
105	 * Initialize the stack protector canary before
106	 * any C code is called.
107	 * ---------------------------------------------
108	 */
109#if STACK_PROTECTOR_ENABLED
110	bl	update_stack_protector_canary
111#endif
112
113	/* ---------------------------------------------
114	 * Perform BL2 setup
115	 * ---------------------------------------------
116	 */
117	mov	r0, r9
118	mov	r1, r10
119	mov	r2, r11
120	mov	r3, r12
121
122	bl	bl2_setup
123
124	/* ---------------------------------------------
125	 * Jump to main function.
126	 * ---------------------------------------------
127	 */
128	bl	bl2_main
129
130	/* ---------------------------------------------
131	 * Should never reach this point.
132	 * ---------------------------------------------
133	 */
134	no_ret	plat_panic_handler
135
136endfunc bl2_entrypoint
137