1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl2_entrypoint) 13 14MEMORY { 15 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 16} 17 18 19SECTIONS 20{ 21 . = BL2_BASE; 22 ASSERT(. == ALIGN(PAGE_SIZE), 23 "BL2_BASE address is not aligned on a page boundary.") 24 25#if SEPARATE_CODE_AND_RODATA 26 .text . : { 27 __TEXT_START__ = .; 28 *bl2_entrypoint.o(.text*) 29 *(SORT_BY_ALIGNMENT(.text*)) 30 *(.vectors) 31 . = ALIGN(PAGE_SIZE); 32 __TEXT_END__ = .; 33 } >RAM 34 35 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 36 .ARM.extab . : { 37 *(.ARM.extab* .gnu.linkonce.armextab.*) 38 } >RAM 39 40 .ARM.exidx . : { 41 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 42 } >RAM 43 44 .rodata . : { 45 __RODATA_START__ = .; 46 *(SORT_BY_ALIGNMENT(.rodata*)) 47 48 RODATA_COMMON 49 50 . = ALIGN(PAGE_SIZE); 51 __RODATA_END__ = .; 52 } >RAM 53#else 54 ro . : { 55 __RO_START__ = .; 56 *bl2_entrypoint.o(.text*) 57 *(SORT_BY_ALIGNMENT(.text*)) 58 *(SORT_BY_ALIGNMENT(.rodata*)) 59 60 RODATA_COMMON 61 62 *(.vectors) 63 __RO_END_UNALIGNED__ = .; 64 /* 65 * Memory page(s) mapped to this section will be marked as 66 * read-only, executable. No RW data from the next section must 67 * creep in. Ensure the rest of the current memory page is unused. 68 */ 69 . = ALIGN(PAGE_SIZE); 70 __RO_END__ = .; 71 } >RAM 72#endif 73 74 /* 75 * Define a linker symbol to mark start of the RW memory area for this 76 * image. 77 */ 78 __RW_START__ = . ; 79 80 DATA_SECTION >RAM 81 STACK_SECTION >RAM 82 BSS_SECTION >RAM 83 XLAT_TABLE_SECTION >RAM 84 85#if USE_COHERENT_MEM 86 /* 87 * The base address of the coherent memory section must be page-aligned (4K) 88 * to guarantee that the coherent data are stored on their own pages and 89 * are not mixed with normal data. This is required to set up the correct 90 * memory attributes for the coherent data page tables. 91 */ 92 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 93 __COHERENT_RAM_START__ = .; 94 *(tzfw_coherent_mem) 95 __COHERENT_RAM_END_UNALIGNED__ = .; 96 /* 97 * Memory page(s) mapped to this section will be marked 98 * as device memory. No other unexpected data must creep in. 99 * Ensure the rest of the current memory page is unused. 100 */ 101 . = ALIGN(PAGE_SIZE); 102 __COHERENT_RAM_END__ = .; 103 } >RAM 104#endif 105 106 /* 107 * Define a linker symbol to mark end of the RW memory area for this 108 * image. 109 */ 110 __RW_END__ = .; 111 __BL2_END__ = .; 112 113 __BSS_SIZE__ = SIZEOF(.bss); 114 115#if USE_COHERENT_MEM 116 __COHERENT_RAM_UNALIGNED_SIZE__ = 117 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 118#endif 119 120 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 121} 122