1/*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <bl32/tsp/tsp.h>
10#include <common/bl_common.h>
11
12	/* ----------------------------------------------------
13	 * The caller-saved registers x0-x18 and LR are saved
14	 * here.
15	 * ----------------------------------------------------
16	 */
17
18#define SCRATCH_REG_SIZE #(20 * 8)
19
20	.macro save_caller_regs_and_lr
21	sub	sp, sp, SCRATCH_REG_SIZE
22	stp	x0, x1, [sp]
23	stp	x2, x3, [sp, #0x10]
24	stp	x4, x5, [sp, #0x20]
25	stp	x6, x7, [sp, #0x30]
26	stp	x8, x9, [sp, #0x40]
27	stp	x10, x11, [sp, #0x50]
28	stp	x12, x13, [sp, #0x60]
29	stp	x14, x15, [sp, #0x70]
30	stp	x16, x17, [sp, #0x80]
31	stp	x18, x30, [sp, #0x90]
32	.endm
33
34	.macro restore_caller_regs_and_lr
35	ldp	x0, x1, [sp]
36	ldp	x2, x3, [sp, #0x10]
37	ldp	x4, x5, [sp, #0x20]
38	ldp	x6, x7, [sp, #0x30]
39	ldp	x8, x9, [sp, #0x40]
40	ldp	x10, x11, [sp, #0x50]
41	ldp	x12, x13, [sp, #0x60]
42	ldp	x14, x15, [sp, #0x70]
43	ldp	x16, x17, [sp, #0x80]
44	ldp	x18, x30, [sp, #0x90]
45	add	sp, sp, SCRATCH_REG_SIZE
46	.endm
47
48	/* ----------------------------------------------------
49	 * Common TSP interrupt handling routine
50	 * ----------------------------------------------------
51	 */
52	.macro	handle_tsp_interrupt label
53	/* Enable the SError interrupt */
54	msr	daifclr, #DAIF_ABT_BIT
55
56	save_caller_regs_and_lr
57	bl	tsp_common_int_handler
58	cbz	x0, interrupt_exit_\label
59
60	/*
61	 * This interrupt was not targetted to S-EL1 so send it to
62	 * the monitor and wait for execution to resume.
63	 */
64	smc	#0
65interrupt_exit_\label:
66	restore_caller_regs_and_lr
67	exception_return
68	.endm
69
70	.globl	tsp_exceptions
71
72	/* -----------------------------------------------------
73	 * TSP exception handlers.
74	 * -----------------------------------------------------
75	 */
76vector_base tsp_exceptions
77	/* -----------------------------------------------------
78	 * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
79	 * are expected and treated as irrecoverable errors.
80	 * -----------------------------------------------------
81	 */
82vector_entry sync_exception_sp_el0
83	b	plat_panic_handler
84end_vector_entry sync_exception_sp_el0
85
86vector_entry irq_sp_el0
87	b	plat_panic_handler
88end_vector_entry irq_sp_el0
89
90vector_entry fiq_sp_el0
91	b	plat_panic_handler
92end_vector_entry fiq_sp_el0
93
94vector_entry serror_sp_el0
95	b	plat_panic_handler
96end_vector_entry serror_sp_el0
97
98
99	/* -----------------------------------------------------
100	 * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
101	 * are expected and handled
102	 * -----------------------------------------------------
103	 */
104vector_entry sync_exception_sp_elx
105	b	plat_panic_handler
106end_vector_entry sync_exception_sp_elx
107
108vector_entry irq_sp_elx
109	handle_tsp_interrupt irq_sp_elx
110end_vector_entry irq_sp_elx
111
112vector_entry fiq_sp_elx
113	handle_tsp_interrupt fiq_sp_elx
114end_vector_entry fiq_sp_elx
115
116vector_entry serror_sp_elx
117	b	plat_panic_handler
118end_vector_entry serror_sp_elx
119
120
121	/* -----------------------------------------------------
122	 * Lower EL using AArch64 : 0x400 - 0x600. No exceptions
123	 * are handled since TSP does not implement a lower EL
124	 * -----------------------------------------------------
125	 */
126vector_entry sync_exception_aarch64
127	b	plat_panic_handler
128end_vector_entry sync_exception_aarch64
129
130vector_entry irq_aarch64
131	b	plat_panic_handler
132end_vector_entry irq_aarch64
133
134vector_entry fiq_aarch64
135	b	plat_panic_handler
136end_vector_entry fiq_aarch64
137
138vector_entry serror_aarch64
139	b	plat_panic_handler
140end_vector_entry serror_aarch64
141
142
143	/* -----------------------------------------------------
144	 * Lower EL using AArch32 : 0x600 - 0x800. No exceptions
145	 * handled since the TSP does not implement a lower EL.
146	 * -----------------------------------------------------
147	 */
148vector_entry sync_exception_aarch32
149	b	plat_panic_handler
150end_vector_entry sync_exception_aarch32
151
152vector_entry irq_aarch32
153	b	plat_panic_handler
154end_vector_entry irq_aarch32
155
156vector_entry fiq_aarch32
157	b	plat_panic_handler
158end_vector_entry fiq_aarch32
159
160vector_entry serror_aarch32
161	b	plat_panic_handler
162end_vector_entry serror_aarch32
163