1Arm FPGA Platform 2================= 3 4This platform supports FPGA images used internally in Arm Ltd., for 5testing and bringup of new cores. With that focus, peripheral support is 6minimal: there is no mass storage or display output, for instance. Also 7this port ignores any power management features of the platform. 8Some interconnect setup is done internally by the platform, so the TF-A code 9just needs to setup UART and GIC. 10 11The FPGA platform requires to pass on a DTB for the non-secure payload 12(mostly Linux), so we let TF-A use information from the DTB for dynamic 13configuration: the UART and GIC base addresses are read from there. 14 15As a result this port is a fairly generic BL31-only port, which can serve 16as a template for a minimal new (and possibly DT-based) platform port. 17 18The aim of this port is to support as many FPGA images as possible with 19a single build. Image specific data must be described in the DTB or should 20be auto-detected at runtime. 21 22As the number and topology layout of the CPU cores differs significantly 23across the various images, this is detected at runtime by BL31. 24The /cpus node in the DT will be added and filled accordingly, as long as 25it does not exist already. 26 27Platform-specific build options 28------------------------------- 29 30- ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers. 31 Normally TF-A panics if it encounters a MPID value not matched to its 32 internal list, but for new or experimental cores this creates a lot of 33 churn. With this option, the code will fall back to some basic CPU support 34 code (only architectural system registers, and no errata). 35 Default value of this flag is 1. 36 37- ``PRELOADED_BL33_BASE`` : Physical address of the BL33 non-secure payload. 38 It must have been loaded into DRAM already, typically this is done by 39 the script that also loads BL31 and the DTB. 40 It defaults to 0x80080000, which is the traditional load address for an 41 arm64 Linux kernel. 42 43- ``FPGA_PRELOADED_DTB_BASE`` : Physical address of the flattened device 44 tree blob (DTB). This DT will be used by TF-A for dynamic configuration, 45 so it must describe at least the UART and a GICv3 interrupt controller. 46 The DT gets amended by the code, to potentially add a command line and 47 fill the CPU topology nodes. It will also be passed on to BL33, by 48 putting its address into the x0 register before jumping to the entry 49 point (following the Linux kernel boot protocol). 50 It defaults to 0x80070000, which is 64KB before the BL33 load address. 51 52- ``FPGA_PRELOADED_CMD_LINE`` : Physical address of the command line to 53 put into the devicetree blob. Due to the lack of a proper bootloader, 54 a command line can be put somewhere into memory, so that BL31 will 55 detect it and copy it into the DTB passed on to BL33. 56 To avoid random garbage, there needs to be a "CMD:" signature before the 57 actual command line. 58 Defaults to 0x1000, which is normally in the "ROM" space of the typical 59 FPGA image (which can be written by the FPGA payload uploader, but is 60 read-only to the CPU). The FPGA payload tool should be given a text file 61 containing the desired command line, prefixed by the "CMD:" signature. 62 63Building the TF-A image 64----------------------- 65 66 .. code:: shell 67 68 make PLAT=arm_fgpa DEBUG=1 69 70 This will use the default load addresses as described above. When those 71 addresses need to differ for a certain setup, they can be passed on the 72 make command line: 73 74 .. code:: shell 75 76 make PLAT=arm_fgpa DEBUG=1 PRELOADED_BL33_BASE=0x80200000 FPGA_PRELOADED_DTB_BASE=0x80180000 bl31 77 78Running the TF-A image 79---------------------- 80 81After building TF-A, the actual TF-A code will be located in ``bl31.bin`` in 82the build directory. 83Additionally there is a ``bl31.axf`` ELF file, which contains BL31, as well 84as some simple ROM trampoline code (required by the Arm FPGA boot flow) and 85a generic DTB to support most of the FPGA images. This can be simply handed 86over to the FPGA payload uploader, which will take care of loading the 87components at their respective load addresses. In addition to this file 88you need at least a BL33 payload (typically a Linux kernel image), optionally 89a Linux initrd image file and possibly a command line: 90 91 .. code:: shell 92 93 fpga-run ... -m bl31.axf -l auto -m Image -l 0x80080000 -m initrd.gz -l 0x84000000 -m cmdline.txt -l 0x1000 94 95-------------- 96 97*Copyright (c) 2020, Arm Limited. All rights reserved.* 98