1 /*
2 * Copyright (C) 2016 - 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 /* IOW unit device driver for Marvell CP110 and CP115 SoCs */
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/marvell/iob.h>
13 #include <lib/mmio.h>
14
15 #include <armada_common.h>
16 #include <mvebu.h>
17 #include <mvebu_def.h>
18
19 #if LOG_LEVEL >= LOG_LEVEL_INFO
20 #define DEBUG_ADDR_MAP
21 #endif
22
23 #define MVEBU_IOB_OFFSET (0x190000)
24 #define MVEBU_IOB_MAX_WINS 16
25
26 /* common defines */
27 #define WIN_ENABLE_BIT (0x1)
28 /* Physical address of the base of the window = {AddrLow[19:0],20`h0} */
29 #define ADDRESS_SHIFT (20 - 4)
30 #define ADDRESS_MASK (0xFFFFFFF0)
31 #define IOB_WIN_ALIGNMENT (0x100000)
32
33 /* IOB registers */
34 #define IOB_WIN_CR_OFFSET(win) (iob_base + 0x0 + (0x20 * win))
35 #define IOB_TARGET_ID_OFFSET (8)
36 #define IOB_TARGET_ID_MASK (0xF)
37
38 #define IOB_WIN_SCR_OFFSET(win) (iob_base + 0x4 + (0x20 * win))
39 #define IOB_WIN_ENA_CTRL_WRITE_SECURE (0x1)
40 #define IOB_WIN_ENA_CTRL_READ_SECURE (0x2)
41 #define IOB_WIN_ENA_WRITE_SECURE (0x4)
42 #define IOB_WIN_ENA_READ_SECURE (0x8)
43
44 #define IOB_WIN_ALR_OFFSET(win) (iob_base + 0x8 + (0x20 * win))
45 #define IOB_WIN_AHR_OFFSET(win) (iob_base + 0xC + (0x20 * win))
46
47 #define IOB_WIN_DIOB_CR_OFFSET(win) (iob_base + 0x10 + (0x20 * win))
48 #define IOB_WIN_XOR0_DIOB_EN BIT(0)
49 #define IOB_WIN_XOR1_DIOB_EN BIT(1)
50
51 uintptr_t iob_base;
52
iob_win_check(struct addr_map_win * win,uint32_t win_num)53 static void iob_win_check(struct addr_map_win *win, uint32_t win_num)
54 {
55 /* check if address is aligned to the size */
56 if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) {
57 win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT);
58 ERROR("Window %d: base address unaligned to 0x%x\n",
59 win_num, IOB_WIN_ALIGNMENT);
60 printf("Align up the base address to 0x%llx\n",
61 win->base_addr);
62 }
63
64 /* size parameter validity check */
65 if (IS_NOT_ALIGN(win->win_size, IOB_WIN_ALIGNMENT)) {
66 win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT);
67 ERROR("Window %d: window size unaligned to 0x%x\n", win_num,
68 IOB_WIN_ALIGNMENT);
69 printf("Aligning size to 0x%llx\n", win->win_size);
70 }
71 }
72
iob_enable_win(struct addr_map_win * win,uint32_t win_id)73 static void iob_enable_win(struct addr_map_win *win, uint32_t win_id)
74 {
75 uint32_t iob_win_reg;
76 uint32_t alr, ahr;
77 uint64_t end_addr;
78 uint32_t reg_en;
79
80 /* move XOR (DMA) to use WIN1 which is used for PCI-EP address space */
81 reg_en = IOB_WIN_XOR0_DIOB_EN | IOB_WIN_XOR1_DIOB_EN;
82 iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(0));
83 iob_win_reg &= ~reg_en;
84 mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(0), iob_win_reg);
85
86 iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(1));
87 iob_win_reg |= reg_en;
88 mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(1), iob_win_reg);
89
90 end_addr = (win->base_addr + win->win_size - 1);
91 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
92 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
93
94 mmio_write_32(IOB_WIN_ALR_OFFSET(win_id), alr);
95 mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr);
96
97 iob_win_reg = WIN_ENABLE_BIT;
98 iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK)
99 << IOB_TARGET_ID_OFFSET;
100 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg);
101
102 }
103
104 #ifdef DEBUG_ADDR_MAP
dump_iob(void)105 static void dump_iob(void)
106 {
107 uint32_t win_id, win_cr, alr, ahr;
108 uint8_t target_id;
109 uint64_t start, end;
110 char *iob_target_name[IOB_MAX_TID] = {
111 "CFG ", "MCI0 ", "PEX1 ", "PEX2 ",
112 "PEX0 ", "NAND ", "RUNIT", "MCI1 " };
113
114 /* Dump all IOB windows */
115 printf("bank id target start end\n");
116 printf("----------------------------------------------------\n");
117 for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
118 win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
119 if (win_cr & WIN_ENABLE_BIT) {
120 target_id = (win_cr >> IOB_TARGET_ID_OFFSET) &
121 IOB_TARGET_ID_MASK;
122 alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id));
123 start = ((uint64_t)alr << ADDRESS_SHIFT);
124 if (win_id != 0) {
125 ahr = mmio_read_32(IOB_WIN_AHR_OFFSET(win_id));
126 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
127 } else {
128 /* Window #0 size is hardcoded to 16MB, as it's
129 * reserved for CP configuration space.
130 */
131 end = start + (16 << 20);
132 }
133 printf("iob %02d %s 0x%016llx 0x%016llx\n",
134 win_id, iob_target_name[target_id],
135 start, end);
136 }
137 }
138 }
139 #endif
140
iob_cfg_space_update(int ap_idx,int cp_idx,uintptr_t base,uintptr_t new_base)141 void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base,
142 uintptr_t new_base)
143 {
144 debug_enter();
145
146 iob_base = base + MVEBU_IOB_OFFSET;
147
148 NOTICE("Change the base address of AP%d-CP%d to %lx\n",
149 ap_idx, cp_idx, new_base);
150 mmio_write_32(IOB_WIN_ALR_OFFSET(0), new_base >> ADDRESS_SHIFT);
151
152 iob_base = new_base + MVEBU_IOB_OFFSET;
153
154 /* Make sure the address was configured by the CPU before
155 * any possible access to the CP.
156 */
157 dsb();
158
159 debug_exit();
160 }
161
init_iob(uintptr_t base)162 int init_iob(uintptr_t base)
163 {
164 struct addr_map_win *win;
165 uint32_t win_id, win_reg;
166 uint32_t win_count;
167
168 INFO("Initializing IOB Address decoding\n");
169
170 /* Get the base address of the address decoding MBUS */
171 iob_base = base + MVEBU_IOB_OFFSET;
172
173 /* Get the array of the windows and fill the map data */
174 marvell_get_iob_memory_map(&win, &win_count, base);
175 if (win_count <= 0) {
176 INFO("no windows configurations found\n");
177 return 0;
178 } else if (win_count > (MVEBU_IOB_MAX_WINS - 1)) {
179 ERROR("IOB mem map array > than max available windows (%d)\n",
180 MVEBU_IOB_MAX_WINS);
181 win_count = MVEBU_IOB_MAX_WINS;
182 }
183
184 /* disable all IOB windows, start from win_id = 1
185 * because can't disable internal register window
186 */
187 for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
188 win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
189 win_reg &= ~WIN_ENABLE_BIT;
190 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), win_reg);
191
192 win_reg = ~IOB_WIN_ENA_CTRL_WRITE_SECURE;
193 win_reg &= ~IOB_WIN_ENA_CTRL_READ_SECURE;
194 win_reg &= ~IOB_WIN_ENA_WRITE_SECURE;
195 win_reg &= ~IOB_WIN_ENA_READ_SECURE;
196 mmio_write_32(IOB_WIN_SCR_OFFSET(win_id), win_reg);
197 }
198
199 for (win_id = 1; win_id < win_count + 1; win_id++, win++) {
200 iob_win_check(win, win_id);
201 iob_enable_win(win, win_id);
202 }
203
204 #ifdef DEBUG_ADDR_MAP
205 dump_iob();
206 #endif
207
208 INFO("Done IOB Address decoding Initializing\n");
209
210 return 0;
211 }
212