1 /* 2 * Copyright 2021 NXP 3 * SPDX-License-Identifier: BSD-3-Clause 4 * 5 */ 6 7 #ifndef CSR_H 8 #define CSR_H 9 10 #define t_anib 0 11 #define t_dbyte 0x10000 12 #define t_master 0x20000 13 #define t_acsm 0x40000 14 #define t_initeng 0x90000 15 #define t_drtub 0xc0000 16 #define t_apbonly 0xd0000 17 #define csr_dbyte_misc_mode_addr 0x00 18 #define csr_micro_cont_mux_sel_addr 0x00 19 #define csr_uct_shadow_regs 0x04 20 #define csr_cal_uclk_info_addr 0x08 21 #define csr_seq0bdly0_addr 0x0b 22 #define csr_seq0bdly1_addr 0x0c 23 #define csr_seq0bdly2_addr 0x0d 24 #define csr_seq0bdly3_addr 0x0e 25 #define csr_seq0bdisable_flag0_addr 0x0c 26 #define csr_seq0bdisable_flag1_addr 0x0d 27 #define csr_seq0bdisable_flag2_addr 0x0e 28 #define csr_seq0bdisable_flag3_addr 0x0f 29 #define csr_seq0bdisable_flag4_addr 0x10 30 #define csr_seq0bdisable_flag5_addr 0x11 31 #define csr_seq0bdisable_flag6_addr 0x12 32 #define csr_seq0bdisable_flag7_addr 0x13 33 #define csr_dfi_mode_addr 0x18 34 #define csr_tristate_mode_ca_addr 0x19 35 #define csr_dfiphyupd_addr 0x21 36 #define csr_dqs_preamble_control_addr 0x24 37 #define csr_master_x4config_addr 0x25 38 #define csr_enable_cs_multicast_addr 0x27 39 #define csr_acx4_anib_dis_addr 0x2c 40 #define csr_dmipin_present_addr 0x2d 41 #define csr_ard_ptr_init_val_addr 0x2e 42 #define csr_dct_write_prot 0x31 43 #define csr_uct_write_only_shadow 0x32 44 #define csr_uct_write_prot 0x33 45 #define csr_uct_dat_write_only_shadow 0x34 46 #define csr_dbyte_dll_mode_cntrl_addr 0x3a 47 #define csr_atx_impedance_addr 0x43 48 #define csr_dq_dqs_rcv_cntrl_addr 0x43 49 #define csr_cal_offsets_addr 0x45 50 #define csr_tx_impedance_ctrl1_addr 0x49 51 #define csr_dq_dqs_rcv_cntrl1_addr 0x4a 52 #define csr_tx_odt_drv_stren_addr 0x4d 53 #define csr_cal_drv_str0_addr 0x50 54 #define csr_atx_slew_rate_addr 0x55 55 #define csr_proc_odt_time_ctl_addr 0x56 56 #define csr_mem_alert_control_addr 0x5b 57 #define csr_mem_alert_control2_addr 0x5c 58 #define csr_tx_slew_rate_addr 0x5f 59 #define csr_mem_reset_l_addr 0x60 60 #define csr_dfi_camode_addr 0x75 61 #define csr_dll_gain_ctl_addr 0x7c 62 #define csr_dll_lockparam_addr 0x7d 63 #define csr_ucclk_hclk_enables_addr 0x80 64 #define csr_acsm_playback0x0_addr 0x80 65 #define csr_acsm_playback1x0_addr 0x81 66 #define csr_cal_rate_addr 0x88 67 #define csr_cal_zap_addr 0x89 68 #define csr_cal_misc2_addr 0x98 69 #define csr_micro_reset_addr 0x99 70 #define csr_dfi_rd_data_cs_dest_map_addr 0xb0 71 #define csr_vref_in_global_addr 0xb2 72 #define csr_dfi_wr_data_cs_dest_map_addr 0xb4 73 #define csr_pll_pwr_dn_addr 0xc3 74 #define csr_pll_ctrl2_addr 0xc5 75 #define csr_pll_ctrl1_addr 0xc7 76 #define csr_pll_test_mode_addr 0xca 77 #define csr_pll_ctrl4_addr 0xcc 78 #define csr_dfi_freq_xlat0_addr 0xf0 79 #define csr_acsm_ctrl0_addr 0xf0 80 #define csr_dfi_freq_ratio_addr 0xfa 81 #define csr_acsm_ctrl13_addr 0xfd 82 #define csr_tx_pre_drv_mode_lsb 8 83 #define csr_tx_pre_n_lsb 4 84 #define csr_tx_pre_p_lsb 0 85 #define csr_atx_pre_drv_mode_lsb 8 86 #define csr_atx_pre_n_lsb 4 87 #define csr_atx_pre_p_lsb 0 88 #define csr_wdqsextension_lsb 8 89 #define csr_lp4sttc_pre_bridge_rx_en_lsb 7 90 #define csr_lp4postamble_ext_lsb 6 91 #define csr_lp4tgl_two_tck_tx_dqs_pre_lsb 5 92 #define csr_position_dfe_init_lsb 2 93 #define csr_two_tck_tx_dqs_pre_lsb 1 94 #define csr_two_tck_rx_dqs_pre_lsb 0 95 #define csr_dll_rx_preamble_mode_lsb 1 96 #define csr_odtstren_n_lsb 6 97 #define csr_drv_stren_fsdq_n_lsb 6 98 #define csr_drv_stren_fsdq_p_lsb 0 99 #define csr_adrv_stren_n_lsb 5 100 #define csr_adrv_stren_p_lsb 0 101 #define csr_cal_drv_str_pu50_lsb 4 102 #define csr_cal_once_lsb 5 103 #define csr_cal_interval_lsb 0 104 #define csr_cal_run_lsb 4 105 #define csr_global_vref_in_dac_lsb 3 106 #define csr_gain_curr_adj_lsb 7 107 #define csr_major_mode_dbyte_lsb 4 108 #define csr_dfe_ctrl_lsb 2 109 #define csr_ext_vref_range_lsb 1 110 #define csr_sel_analog_vref_lsb 0 111 #define csr_malertsync_bypass_lsb 0 112 #define csr_ck_dis_val_lsb 2 113 #define csr_ddr2tmode_lsb 1 114 #define csr_dis_dyn_adr_tri_lsb 0 115 #define csr_dbyte_disable_lsb 2 116 #define csr_power_down_rcvr_lsb 0 117 #define csr_power_down_rcvr_dqs_lsb 9 118 #define csr_rx_pad_standby_en_lsb 10 119 #define csr_rx_pad_standby_en_mask 0x400 120 #define csr_x4tg_lsb 0 121 #define csr_reset_to_micro_mask 0x8 122 #define csr_protect_mem_reset_mask 0x2 123 #define csr_stall_to_micro_mask 0x1 124 #define uct_write_prot_shadow_mask 0x1 125 #define csr_acsm_par_mode_mask 0x4000 126 #define csr_acsm_cke_enb_lsb 0 127 #define csr_dfiphyupd_threshold_lsb 8 128 #define csr_dfiphyupd_threshold_msb 11 129 #define csr_dfiphyupd_threshold_mask 0xf00 130 #define csr_dfi_rd_destm0_lsb 0 131 #define csr_dfi_rd_destm1_lsb 2 132 #define csr_dfi_rd_destm2_lsb 4 133 #define csr_dfi_rd_destm3_lsb 6 134 #define csr_dfi_wr_destm0_lsb 0 135 #define csr_dfi_wr_destm1_lsb 2 136 #define csr_dfi_wr_destm2_lsb 4 137 #define csr_dfi_wr_destm3_lsb 6 138 #define csr_acsm_2t_mode_mask 0x40 139 #define csr_cal_misc2_err_dis 13 140 #define csr_cal_offset_pdc_lsb 6 141 #define csr_cal_offset_pdc_msb 9 142 #define csr_cal_offset_pdc_mask 0xe0 143 #define csr_cal_drv_pdth_mask 0x3c0 144 145 146 struct impedance_mapping { 147 int ohm; 148 int code; 149 }; 150 151 #endif 152