1/*
2 * Copyright (c) 2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	compatible = "arm,Corstone-700";
11	interrupt-parent = <&gic>;
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	chosen { };
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,armv8";
24			reg = <0>;
25			next-level-cache = <&L2_0>;
26		};
27	};
28
29	memory@80000000 {
30		device_type = "memory";
31		reg = <0x80000000 0x80000000>;
32	};
33
34	gic: interrupt-controller@1c000000 {
35		compatible = "arm,gic-400";
36		#interrupt-cells = <3>;
37		#address-cells = <0>;
38		interrupt-controller;
39		reg =	<0x1c010000 0x1000>,
40			<0x1c02f000 0x2000>,
41			<0x1c04f000 0x1000>,
42			<0x1c06f000 0x2000>;
43		interrupts = <1 9 0xf08>;
44	};
45
46	L2_0: l2-cache0 {
47		compatible = "cache";
48	};
49
50	refclk100mhz: refclk100mhz {
51		compatible = "fixed-clock";
52		#clock-cells = <0>;
53		clock-frequency = <100000000>;
54		clock-output-names = "apb_pclk";
55	};
56
57	smbclk: refclk24mhzx2 {
58		/* Reference 24MHz clock x 2 */
59		compatible = "fixed-clock";
60		#clock-cells = <0>;
61		clock-frequency = <48000000>;
62		clock-output-names = "smclk";
63	};
64
65	uartclk: uartclk {
66		/* UART clock - 32MHz */
67		compatible = "fixed-clock";
68		#clock-cells = <0>;
69		clock-frequency = <32000000>;
70		clock-output-names = "uartclk";
71	};
72
73	serial0: uart@1a510000 {
74		compatible = "arm,pl011", "arm,primecell";
75		reg = <0x1a510000 0x1000>;
76		interrupt-parent = <&gic>;
77		interrupts = <0 19 4>;
78		clocks = <&uartclk>, <&refclk100mhz>;
79		clock-names = "uartclk", "apb_pclk";
80	};
81
82	serial1: uart@1a520000 {
83		compatible = "arm,pl011", "arm,primecell";
84		reg = <0x1a520000 0x1000>;
85		interrupt-parent = <&gic>;
86		interrupts = <0 20 4>;
87		clocks = <&uartclk>, <&refclk100mhz>;
88		clock-names = "uartclk", "apb_pclk";
89	};
90
91	timer {
92		compatible = "arm,armv8-timer";
93		interrupts =	<1 13 0xf08>,
94				<1 14 0xf08>,
95				<1 11 0xf08>,
96				<1 10 0xf08>;
97	};
98
99	refclk: refclk@1a220000 {
100		compatible = "arm,armv7-timer-mem";
101		reg = <0x1a220000  0x1000>;
102		#address-cells = <1>;
103		#size-cells = <1>;
104		ranges;
105
106		frame@1a230000 {
107			frame-number = <0>;
108			interrupts = <0 2 0xf04>;
109			reg = <0x1a230000 0x1000>;
110		};
111	};
112
113	mbox_es0mhu0: mhu@1b000000 {
114		compatible = "arm,mhuv2","arm,primecell";
115		reg = <0x1b000000 0x1000>,
116		      <0x1b010000 0x1000>;
117		clocks = <&refclk100mhz>;
118		clock-names = "apb_pclk";
119		interrupts = <0 12 4>;
120		interrupt-names = "mhu_rx";
121		#mbox-cells = <1>;
122		mbox-name = "arm-es0-mhu0";
123	};
124
125	mbox_es0mhu1: mhu@1b020000 {
126		compatible = "arm,mhuv2","arm,primecell";
127		reg = <0x1b020000 0x1000>,
128		      <0x1b030000 0x1000>;
129		clocks = <&refclk100mhz>;
130		clock-names = "apb_pclk";
131		interrupts = <0 47 4>;
132		interrupt-names = "mhu_rx";
133		#mbox-cells = <1>;
134		mbox-name = "arm-es0-mhu1";
135	};
136
137	mbox_semhu1: mhu@1b820000 {
138		compatible = "arm,mhuv2","arm,primecell";
139		reg = <0x1b820000 0x1000>,
140		      <0x1b830000 0x1000>;
141		clocks = <&refclk100mhz>;
142		clock-names = "apb_pclk";
143		interrupts = <0 45 4>;
144		interrupt-names = "mhu_rx";
145		#mbox-cells = <1>;
146		mbox-name = "arm-se-mhu1";
147	};
148
149	client {
150		compatible = "arm,client";
151		mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>;
152		mbox-names = "es0mhu0", "es0mhu1", "semhu1";
153	};
154
155	extsys0: extsys@1A010310 {
156		compatible = "arm,extsys_ctrl";
157		reg = <0x1A010310 0x4>,
158		      <0x1A010314 0x4>;
159		reg-names = "rstreg", "streg";
160	};
161};
162