1/*
2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <services/sdei_flags.h>
9
10#define LEVEL	0
11#define EDGE	2
12#define SDEI_NORMAL	0x70
13#define HIGHEST_SEC	0
14
15/memreserve/ 0x80000000 0x00010000;
16
17/ {
18};
19
20/ {
21	model = "FVP Base";
22	compatible = "arm,vfp-base", "arm,vexpress";
23	interrupt-parent = <&gic>;
24	#address-cells = <2>;
25	#size-cells = <2>;
26
27	chosen { };
28
29	aliases {
30		serial0 = &v2m_serial0;
31		serial1 = &v2m_serial1;
32		serial2 = &v2m_serial2;
33		serial3 = &v2m_serial3;
34	};
35
36	psci {
37		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
38		method = "smc";
39		cpu_suspend = <0xc4000001>;
40		cpu_off = <0x84000002>;
41		cpu_on = <0xc4000003>;
42		sys_poweroff = <0x84000008>;
43		sys_reset = <0x84000009>;
44		max-pwr-lvl = <2>;
45	};
46
47#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF
48	firmware {
49#if SDEI_IN_FCONF
50		sdei {
51			compatible = "arm,sdei-1.0";
52			method = "smc";
53			private_event_count = <3>;
54			shared_event_count = <3>;
55			/*
56			 * Each event descriptor has typically 3 fields:
57			 * 1. Event number
58			 * 2. Interrupt number the event is bound to or
59			 *    if event is dynamic, specified as SDEI_DYN_IRQ
60			 * 3. Bit map of event flags
61			 */
62			private_events =	<1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
63						<1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
64						<1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
65			shared_events =		<2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
66						<2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
67						<2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
68		};
69#endif /* SDEI_IN_FCONF */
70
71#if SEC_INT_DESC_IN_FCONF
72		sec_interrupts {
73			compatible = "arm,secure_interrupt_desc";
74			/* Number of G0 and G1 secure interrupts defined by the platform */
75			g0_intr_cnt = <2>;
76			g1s_intr_cnt = <9>;
77			/*
78			 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
79			 * terminology. Each interrupt property descriptor has 3 fields:
80			 * 1. Interrupt number
81			 * 2. Interrupt priority
82			 * 3. Type of interrupt (Edge or Level configured)
83			 */
84			g0_intr_desc =	< 8 SDEI_NORMAL EDGE>,
85					<14 HIGHEST_SEC EDGE>;
86
87			g1s_intr_desc =	< 9 HIGHEST_SEC EDGE>,
88					<10 HIGHEST_SEC EDGE>,
89					<11 HIGHEST_SEC EDGE>,
90					<12 HIGHEST_SEC EDGE>,
91					<13 HIGHEST_SEC EDGE>,
92					<15 HIGHEST_SEC EDGE>,
93					<29 HIGHEST_SEC LEVEL>,
94					<56 HIGHEST_SEC LEVEL>,
95					<57 HIGHEST_SEC LEVEL>;
96		};
97#endif /* SEC_INT_DESC_IN_FCONF */
98	};
99#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */
100
101	cpus {
102		#address-cells = <2>;
103		#size-cells = <0>;
104
105		CPU_MAP
106
107		idle-states {
108			entry-method = "arm,psci";
109
110			CPU_SLEEP_0: cpu-sleep-0 {
111				compatible = "arm,idle-state";
112				local-timer-stop;
113				arm,psci-suspend-param = <0x0010000>;
114				entry-latency-us = <40>;
115				exit-latency-us = <100>;
116				min-residency-us = <150>;
117			};
118
119			CLUSTER_SLEEP_0: cluster-sleep-0 {
120				compatible = "arm,idle-state";
121				local-timer-stop;
122				arm,psci-suspend-param = <0x1010000>;
123				entry-latency-us = <500>;
124				exit-latency-us = <1000>;
125				min-residency-us = <2500>;
126			};
127		};
128
129		CPUS
130
131		L2_0: l2-cache0 {
132			compatible = "cache";
133		};
134	};
135
136	memory@80000000 {
137		device_type = "memory";
138		reg = <0x00000000 0x80000000 0 0x7F000000>,
139		      <0x00000008 0x80000000 0 0x80000000>;
140	};
141
142	gic: interrupt-controller@2f000000 {
143		compatible = "arm,gic-v3";
144		#interrupt-cells = <3>;
145		#address-cells = <2>;
146		#size-cells = <2>;
147		ranges;
148		interrupt-controller;
149		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
150		      <0x0 0x2f100000 0 0x200000>,	// GICR
151		      <0x0 0x2c000000 0 0x2000>,	// GICC
152		      <0x0 0x2c010000 0 0x2000>,	// GICH
153		      <0x0 0x2c02f000 0 0x2000>;	// GICV
154		interrupts = <1 9 4>;
155
156		its: its@2f020000 {
157			compatible = "arm,gic-v3-its";
158			msi-controller;
159			reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
160		};
161	};
162
163	timer {
164		compatible = "arm,armv8-timer";
165		interrupts = <GIC_PPI 13
166				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
167			     <GIC_PPI 14
168				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
169			     <GIC_PPI 11
170				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
171			     <GIC_PPI 10
172				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
173		clock-frequency = <100000000>;
174	};
175
176	timer@2a810000 {
177			compatible = "arm,armv7-timer-mem";
178			reg = <0x0 0x2a810000 0x0 0x10000>;
179			clock-frequency = <100000000>;
180			#address-cells = <2>;
181			#size-cells = <2>;
182			ranges;
183			frame@2a830000 {
184				frame-number = <1>;
185				interrupts = <0 26 4>;
186				reg = <0x0 0x2a830000 0x0 0x10000>;
187			};
188	};
189
190	pmu {
191		compatible = "arm,armv8-pmuv3";
192		interrupts = <0 60 4>,
193			     <0 61 4>,
194			     <0 62 4>,
195			     <0 63 4>;
196	};
197
198	smb@0,0 {
199		compatible = "simple-bus";
200
201		#address-cells = <2>;
202		#size-cells = <1>;
203		ranges = <0 0 0 0x08000000 0x04000000>,
204			 <1 0 0 0x14000000 0x04000000>,
205			 <2 0 0 0x18000000 0x04000000>,
206			 <3 0 0 0x1c000000 0x04000000>,
207			 <4 0 0 0x0c000000 0x04000000>,
208			 <5 0 0 0x10000000 0x04000000>;
209
210		#include "rtsm_ve-motherboard.dtsi"
211	};
212
213	panels {
214		panel {
215			compatible	= "panel";
216			mode		= "XVGA";
217			refresh		= <60>;
218			xres		= <1024>;
219			yres		= <768>;
220			pixclock	= <15748>;
221			left_margin	= <152>;
222			right_margin	= <48>;
223			upper_margin	= <23>;
224			lower_margin	= <3>;
225			hsync_len	= <104>;
226			vsync_len	= <4>;
227			sync		= <0>;
228			vmode		= "FB_VMODE_NONINTERLACED";
229			tim2		= "TIM2_BCD", "TIM2_IPC";
230			cntl		= "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
231			caps		= "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
232			bpp		= <16>;
233		};
234	};
235};
236