1/*
2 * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
10	model = "V2F-1XV7 Cortex-A7x1 SMM";
11	compatible = "arm,vexpress,v2f-1xv7", "arm,vexpress";
12	interrupt-parent = <&gic>;
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	cpus {
17		#address-cells = <2>;
18		#size-cells = <0>;
19
20		cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a7";
23			reg = <0 0>;
24		};
25	};
26
27	memory@0,80000000 {
28		device_type = "memory";
29		reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
30	};
31
32	gic: interrupt-controller@2c001000 {
33		compatible = "arm,cortex-a15-gic";
34		#interrupt-cells = <3>;
35		#address-cells = <0>;
36		interrupt-controller;
37		reg = <0 0x2c001000 0 0x1000>,
38		      <0 0x2c002000 0 0x1000>,
39		      <0 0x2c004000 0 0x2000>,
40		      <0 0x2c006000 0 0x2000>;
41		interrupts = <1 9 0xf04>;
42	};
43
44	smbclk: refclk24mhzx2 {
45		/* Reference 24MHz clock x 2 */
46		compatible = "fixed-clock";
47		#clock-cells = <0>;
48		clock-frequency = <48000000>;
49		clock-output-names = "smclk";
50	};
51
52	smb {
53		compatible = "simple-bus";
54
55		#address-cells = <2>;
56		#size-cells = <1>;
57		ranges = <0 0 0 0x08000000 0x04000000>,
58			 <1 0 0 0x14000000 0x04000000>,
59			 <2 0 0 0x18000000 0x04000000>,
60			 <3 0 0 0x1c000000 0x04000000>,
61			 <4 0 0 0x0c000000 0x04000000>,
62			 <5 0 0 0x10000000 0x04000000>;
63
64		#interrupt-cells = <1>;
65		interrupt-map-mask = <0 0 63>;
66		interrupt-map = <0 0  0 &gic 0  0 4>,
67				<0 0  1 &gic 0  1 4>,
68				<0 0  2 &gic 0  2 4>,
69				<0 0  3 &gic 0  3 4>,
70				<0 0  4 &gic 0  4 4>,
71				<0 0  5 &gic 0  5 4>,
72				<0 0 42 &gic 0 42 4>;
73
74		#include "rtsm_ve-motherboard-aarch32.dtsi"
75	};
76};
77