1/*
2 * Copyright (c) 2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8#include "morello.dtsi"
9
10/ {
11
12	chosen {
13		stdout-path = "serial0:115200n8";
14	};
15
16	reserved-memory {
17		#address-cells = <2>;
18		#size-cells = <2>;
19		ranges;
20
21		secure-firmware@ff000000 {
22			reg = <0 0xff000000 0 0x01000000>;
23			no-map;
24		};
25	};
26
27	cpus {
28		#address-cells = <2>;
29		#size-cells = <0>;
30
31		cpu-map {
32			cluster0 {
33				core0 {
34					cpu = <&CPU0>;
35				};
36				core1 {
37					cpu = <&CPU1>;
38				};
39			};
40			cluster1 {
41				core0 {
42					cpu = <&CPU2>;
43				};
44				core1 {
45					cpu = <&CPU3>;
46				};
47			};
48		};
49		CPU0: cpu0@0 {
50			compatible = "arm,armv8";
51			reg = <0x0 0x0>;
52			device_type = "cpu";
53			enable-method = "psci";
54			clocks = <&scmi_dvfs 0>;
55		};
56		CPU1: cpu1@100 {
57			compatible = "arm,armv8";
58			reg = <0x0 0x100>;
59			device_type = "cpu";
60			enable-method = "psci";
61			clocks = <&scmi_dvfs 0>;
62		};
63		CPU2: cpu2@10000 {
64			compatible = "arm,armv8";
65			reg = <0x0 0x10000>;
66			device_type = "cpu";
67			enable-method = "psci";
68			clocks = <&scmi_dvfs 1>;
69		};
70		CPU3: cpu3@10100 {
71			compatible = "arm,armv8";
72			reg = <0x0 0x10100>;
73			device_type = "cpu";
74			enable-method = "psci";
75			clocks = <&scmi_dvfs 1>;
76		};
77	};
78
79	/* The first bank of memory, memory map is actually provided by UEFI. */
80	memory@80000000 {
81		#address-cells = <2>;
82		#size-cells = <2>;
83		device_type = "memory";
84		/* [0x80000000-0xffffffff] */
85		reg = <0x00000000 0x80000000 0x0 0x80000000>;
86	};
87
88	memory@8080000000 {
89		#address-cells = <2>;
90		#size-cells = <2>;
91		device_type = "memory";
92		/* [0x8080000000-0x83ffffffff] */
93		reg = <0x00000080 0x80000000 0x1 0x80000000>;
94	};
95
96	virtio_block@1c170000 {
97		compatible = "virtio,mmio";
98		reg = <0x0 0x1c170000 0x0 0x200>;
99		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
100	};
101
102	virtio_net@1c180000 {
103		compatible = "virtio,mmio";
104		reg = <0x0 0x1c180000 0x0 0x200>;
105		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
106	};
107
108	virtio_rng@1c190000 {
109		compatible = "virtio,mmio";
110		reg = <0x0 0x1c190000 0x0 0x200>;
111		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
112	};
113
114	virtio_p9@1c1a0000 {
115		compatible = "virtio,mmio";
116		reg = <0x0 0x1c1a0000 0x0 0x200>;
117		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
118	};
119
120	ethernet@1d100000 {
121		compatible = "smsc,lan91c111";
122		reg = <0x0 0x1d100000 0x0 0x10000>;
123		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
124	};
125
126	kmi@1c150000 {
127		compatible = "arm,pl050", "arm,primecell";
128		reg = <0x0 0x1c150000 0x0 0x1000>;
129		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
130		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
131		clock-names = "KMIREFCLK", "apb_pclk";
132	};
133
134	kmi@1c160000 {
135		compatible = "arm,pl050", "arm,primecell";
136		reg = <0x0 0x1c160000 0x0 0x1000>;
137		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
138		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
139		clock-names = "KMIREFCLK", "apb_pclk";
140	};
141
142	firmware {
143		scmi {
144			compatible = "arm,scmi";
145			mbox-names = "tx", "rx";
146			mboxes = <&mailbox 1 0 &mailbox 1 1>;
147			shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
148			#address-cells = <1>;
149			#size-cells = <0>;
150
151			scmi_dvfs: protocol@13 {
152				reg = <0x13>;
153				#clock-cells = <1>;
154			};
155		};
156	};
157
158	bp_clock24mhz: clock24mhz {
159		compatible = "fixed-clock";
160		#clock-cells = <0>;
161		clock-frequency = <24000000>;
162		clock-output-names = "bp:clock24mhz";
163	};
164};
165
166&gic {
167	reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
168	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
169	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
170};
171