1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 6/ { 7 soc { 8 ddr: ddr@5a003000{ 9 10 compatible = "st,stm32mp1-ddr"; 11 12 reg = <0x5A003000 0x550 13 0x5A004000 0x234>; 14 15 clocks = <&rcc AXIDCG>, 16 <&rcc DDRC1>, 17 <&rcc DDRC2>, 18 <&rcc DDRPHYC>, 19 <&rcc DDRCAPB>, 20 <&rcc DDRPHYCAPB>; 21 22 clock-names = "axidcg", 23 "ddrc1", 24 "ddrc2", 25 "ddrphyc", 26 "ddrcapb", 27 "ddrphycapb"; 28 29 st,mem-name = DDR_MEM_NAME; 30 st,mem-speed = <DDR_MEM_SPEED>; 31 st,mem-size = <DDR_MEM_SIZE>; 32 33 st,ctl-reg = < 34 DDR_MSTR 35 DDR_MRCTRL0 36 DDR_MRCTRL1 37 DDR_DERATEEN 38 DDR_DERATEINT 39 DDR_PWRCTL 40 DDR_PWRTMG 41 DDR_HWLPCTL 42 DDR_RFSHCTL0 43 DDR_RFSHCTL3 44 DDR_CRCPARCTL0 45 DDR_ZQCTL0 46 DDR_DFITMG0 47 DDR_DFITMG1 48 DDR_DFILPCFG0 49 DDR_DFIUPD0 50 DDR_DFIUPD1 51 DDR_DFIUPD2 52 DDR_DFIPHYMSTR 53 DDR_ODTMAP 54 DDR_DBG0 55 DDR_DBG1 56 DDR_DBGCMD 57 DDR_POISONCFG 58 DDR_PCCFG 59 >; 60 61 st,ctl-timing = < 62 DDR_RFSHTMG 63 DDR_DRAMTMG0 64 DDR_DRAMTMG1 65 DDR_DRAMTMG2 66 DDR_DRAMTMG3 67 DDR_DRAMTMG4 68 DDR_DRAMTMG5 69 DDR_DRAMTMG6 70 DDR_DRAMTMG7 71 DDR_DRAMTMG8 72 DDR_DRAMTMG14 73 DDR_ODTCFG 74 >; 75 76 st,ctl-map = < 77 DDR_ADDRMAP1 78 DDR_ADDRMAP2 79 DDR_ADDRMAP3 80 DDR_ADDRMAP4 81 DDR_ADDRMAP5 82 DDR_ADDRMAP6 83 DDR_ADDRMAP9 84 DDR_ADDRMAP10 85 DDR_ADDRMAP11 86 >; 87 88 st,ctl-perf = < 89 DDR_SCHED 90 DDR_SCHED1 91 DDR_PERFHPR1 92 DDR_PERFLPR1 93 DDR_PERFWR1 94 DDR_PCFGR_0 95 DDR_PCFGW_0 96 DDR_PCFGQOS0_0 97 DDR_PCFGQOS1_0 98 DDR_PCFGWQOS0_0 99 DDR_PCFGWQOS1_0 100 DDR_PCFGR_1 101 DDR_PCFGW_1 102 DDR_PCFGQOS0_1 103 DDR_PCFGQOS1_1 104 DDR_PCFGWQOS0_1 105 DDR_PCFGWQOS1_1 106 >; 107 108 st,phy-reg = < 109 DDR_PGCR 110 DDR_ACIOCR 111 DDR_DXCCR 112 DDR_DSGCR 113 DDR_DCR 114 DDR_ODTCR 115 DDR_ZQ0CR1 116 DDR_DX0GCR 117 DDR_DX1GCR 118 DDR_DX2GCR 119 DDR_DX3GCR 120 >; 121 122 st,phy-timing = < 123 DDR_PTR0 124 DDR_PTR1 125 DDR_PTR2 126 DDR_DTPR0 127 DDR_DTPR1 128 DDR_DTPR2 129 DDR_MR0 130 DDR_MR1 131 DDR_MR2 132 DDR_MR3 133 >; 134 135 st,phy-cal = < 136 DDR_DX0DLLCR 137 DDR_DX0DQTR 138 DDR_DX0DQSTR 139 DDR_DX1DLLCR 140 DDR_DX1DQTR 141 DDR_DX1DQSTR 142 DDR_DX2DLLCR 143 DDR_DX2DQTR 144 DDR_DX2DQSTR 145 DDR_DX3DLLCR 146 DDR_DX3DQTR 147 DDR_DX3DQSTR 148 >; 149 150 status = "okay"; 151 }; 152 }; 153}; 154