1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 4 */ 5 6 #ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ 7 #define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ 8 9 /* PLL output is enable when x=1, with x=p,q or r */ 10 #define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) 11 12 /* st,clksrc: mandatory clock source */ 13 14 #define CLK_MPU_HSI 0x00000200 15 #define CLK_MPU_HSE 0x00000201 16 #define CLK_MPU_PLL1P 0x00000202 17 #define CLK_MPU_PLL1P_DIV 0x00000203 18 19 #define CLK_AXI_HSI 0x00000240 20 #define CLK_AXI_HSE 0x00000241 21 #define CLK_AXI_PLL2P 0x00000242 22 23 #define CLK_MCU_HSI 0x00000480 24 #define CLK_MCU_HSE 0x00000481 25 #define CLK_MCU_CSI 0x00000482 26 #define CLK_MCU_PLL3P 0x00000483 27 28 #define CLK_PLL12_HSI 0x00000280 29 #define CLK_PLL12_HSE 0x00000281 30 31 #define CLK_PLL3_HSI 0x00008200 32 #define CLK_PLL3_HSE 0x00008201 33 #define CLK_PLL3_CSI 0x00008202 34 35 #define CLK_PLL4_HSI 0x00008240 36 #define CLK_PLL4_HSE 0x00008241 37 #define CLK_PLL4_CSI 0x00008242 38 #define CLK_PLL4_I2SCKIN 0x00008243 39 40 #define CLK_RTC_DISABLED 0x00001400 41 #define CLK_RTC_LSE 0x00001401 42 #define CLK_RTC_LSI 0x00001402 43 #define CLK_RTC_HSE 0x00001403 44 45 #define CLK_MCO1_HSI 0x00008000 46 #define CLK_MCO1_HSE 0x00008001 47 #define CLK_MCO1_CSI 0x00008002 48 #define CLK_MCO1_LSI 0x00008003 49 #define CLK_MCO1_LSE 0x00008004 50 #define CLK_MCO1_DISABLED 0x0000800F 51 52 #define CLK_MCO2_MPU 0x00008040 53 #define CLK_MCO2_AXI 0x00008041 54 #define CLK_MCO2_MCU 0x00008042 55 #define CLK_MCO2_PLL4P 0x00008043 56 #define CLK_MCO2_HSE 0x00008044 57 #define CLK_MCO2_HSI 0x00008045 58 #define CLK_MCO2_DISABLED 0x0000804F 59 60 /* st,pkcs: peripheral kernel clock source */ 61 62 #define CLK_I2C12_PCLK1 0x00008C00 63 #define CLK_I2C12_PLL4R 0x00008C01 64 #define CLK_I2C12_HSI 0x00008C02 65 #define CLK_I2C12_CSI 0x00008C03 66 #define CLK_I2C12_DISABLED 0x00008C07 67 68 #define CLK_I2C35_PCLK1 0x00008C40 69 #define CLK_I2C35_PLL4R 0x00008C41 70 #define CLK_I2C35_HSI 0x00008C42 71 #define CLK_I2C35_CSI 0x00008C43 72 #define CLK_I2C35_DISABLED 0x00008C47 73 74 #define CLK_I2C46_PCLK5 0x00000C00 75 #define CLK_I2C46_PLL3Q 0x00000C01 76 #define CLK_I2C46_HSI 0x00000C02 77 #define CLK_I2C46_CSI 0x00000C03 78 #define CLK_I2C46_DISABLED 0x00000C07 79 80 #define CLK_SAI1_PLL4Q 0x00008C80 81 #define CLK_SAI1_PLL3Q 0x00008C81 82 #define CLK_SAI1_I2SCKIN 0x00008C82 83 #define CLK_SAI1_CKPER 0x00008C83 84 #define CLK_SAI1_PLL3R 0x00008C84 85 #define CLK_SAI1_DISABLED 0x00008C87 86 87 #define CLK_SAI2_PLL4Q 0x00008CC0 88 #define CLK_SAI2_PLL3Q 0x00008CC1 89 #define CLK_SAI2_I2SCKIN 0x00008CC2 90 #define CLK_SAI2_CKPER 0x00008CC3 91 #define CLK_SAI2_SPDIF 0x00008CC4 92 #define CLK_SAI2_PLL3R 0x00008CC5 93 #define CLK_SAI2_DISABLED 0x00008CC7 94 95 #define CLK_SAI3_PLL4Q 0x00008D00 96 #define CLK_SAI3_PLL3Q 0x00008D01 97 #define CLK_SAI3_I2SCKIN 0x00008D02 98 #define CLK_SAI3_CKPER 0x00008D03 99 #define CLK_SAI3_PLL3R 0x00008D04 100 #define CLK_SAI3_DISABLED 0x00008D07 101 102 #define CLK_SAI4_PLL4Q 0x00008D40 103 #define CLK_SAI4_PLL3Q 0x00008D41 104 #define CLK_SAI4_I2SCKIN 0x00008D42 105 #define CLK_SAI4_CKPER 0x00008D43 106 #define CLK_SAI4_PLL3R 0x00008D44 107 #define CLK_SAI4_DISABLED 0x00008D47 108 109 #define CLK_SPI2S1_PLL4P 0x00008D80 110 #define CLK_SPI2S1_PLL3Q 0x00008D81 111 #define CLK_SPI2S1_I2SCKIN 0x00008D82 112 #define CLK_SPI2S1_CKPER 0x00008D83 113 #define CLK_SPI2S1_PLL3R 0x00008D84 114 #define CLK_SPI2S1_DISABLED 0x00008D87 115 116 #define CLK_SPI2S23_PLL4P 0x00008DC0 117 #define CLK_SPI2S23_PLL3Q 0x00008DC1 118 #define CLK_SPI2S23_I2SCKIN 0x00008DC2 119 #define CLK_SPI2S23_CKPER 0x00008DC3 120 #define CLK_SPI2S23_PLL3R 0x00008DC4 121 #define CLK_SPI2S23_DISABLED 0x00008DC7 122 123 #define CLK_SPI45_PCLK2 0x00008E00 124 #define CLK_SPI45_PLL4Q 0x00008E01 125 #define CLK_SPI45_HSI 0x00008E02 126 #define CLK_SPI45_CSI 0x00008E03 127 #define CLK_SPI45_HSE 0x00008E04 128 #define CLK_SPI45_DISABLED 0x00008E07 129 130 #define CLK_SPI6_PCLK5 0x00000C40 131 #define CLK_SPI6_PLL4Q 0x00000C41 132 #define CLK_SPI6_HSI 0x00000C42 133 #define CLK_SPI6_CSI 0x00000C43 134 #define CLK_SPI6_HSE 0x00000C44 135 #define CLK_SPI6_PLL3Q 0x00000C45 136 #define CLK_SPI6_DISABLED 0x00000C47 137 138 #define CLK_UART6_PCLK2 0x00008E40 139 #define CLK_UART6_PLL4Q 0x00008E41 140 #define CLK_UART6_HSI 0x00008E42 141 #define CLK_UART6_CSI 0x00008E43 142 #define CLK_UART6_HSE 0x00008E44 143 #define CLK_UART6_DISABLED 0x00008E47 144 145 #define CLK_UART24_PCLK1 0x00008E80 146 #define CLK_UART24_PLL4Q 0x00008E81 147 #define CLK_UART24_HSI 0x00008E82 148 #define CLK_UART24_CSI 0x00008E83 149 #define CLK_UART24_HSE 0x00008E84 150 #define CLK_UART24_DISABLED 0x00008E87 151 152 #define CLK_UART35_PCLK1 0x00008EC0 153 #define CLK_UART35_PLL4Q 0x00008EC1 154 #define CLK_UART35_HSI 0x00008EC2 155 #define CLK_UART35_CSI 0x00008EC3 156 #define CLK_UART35_HSE 0x00008EC4 157 #define CLK_UART35_DISABLED 0x00008EC7 158 159 #define CLK_UART78_PCLK1 0x00008F00 160 #define CLK_UART78_PLL4Q 0x00008F01 161 #define CLK_UART78_HSI 0x00008F02 162 #define CLK_UART78_CSI 0x00008F03 163 #define CLK_UART78_HSE 0x00008F04 164 #define CLK_UART78_DISABLED 0x00008F07 165 166 #define CLK_UART1_PCLK5 0x00000C80 167 #define CLK_UART1_PLL3Q 0x00000C81 168 #define CLK_UART1_HSI 0x00000C82 169 #define CLK_UART1_CSI 0x00000C83 170 #define CLK_UART1_PLL4Q 0x00000C84 171 #define CLK_UART1_HSE 0x00000C85 172 #define CLK_UART1_DISABLED 0x00000C87 173 174 #define CLK_SDMMC12_HCLK6 0x00008F40 175 #define CLK_SDMMC12_PLL3R 0x00008F41 176 #define CLK_SDMMC12_PLL4P 0x00008F42 177 #define CLK_SDMMC12_HSI 0x00008F43 178 #define CLK_SDMMC12_DISABLED 0x00008F47 179 180 #define CLK_SDMMC3_HCLK2 0x00008F80 181 #define CLK_SDMMC3_PLL3R 0x00008F81 182 #define CLK_SDMMC3_PLL4P 0x00008F82 183 #define CLK_SDMMC3_HSI 0x00008F83 184 #define CLK_SDMMC3_DISABLED 0x00008F87 185 186 #define CLK_ETH_PLL4P 0x00008FC0 187 #define CLK_ETH_PLL3Q 0x00008FC1 188 #define CLK_ETH_DISABLED 0x00008FC3 189 190 #define CLK_QSPI_ACLK 0x00009000 191 #define CLK_QSPI_PLL3R 0x00009001 192 #define CLK_QSPI_PLL4P 0x00009002 193 #define CLK_QSPI_CKPER 0x00009003 194 195 #define CLK_FMC_ACLK 0x00009040 196 #define CLK_FMC_PLL3R 0x00009041 197 #define CLK_FMC_PLL4P 0x00009042 198 #define CLK_FMC_CKPER 0x00009043 199 200 #define CLK_FDCAN_HSE 0x000090C0 201 #define CLK_FDCAN_PLL3Q 0x000090C1 202 #define CLK_FDCAN_PLL4Q 0x000090C2 203 #define CLK_FDCAN_PLL4R 0x000090C3 204 205 #define CLK_SPDIF_PLL4P 0x00009140 206 #define CLK_SPDIF_PLL3Q 0x00009141 207 #define CLK_SPDIF_HSI 0x00009142 208 #define CLK_SPDIF_DISABLED 0x00009143 209 210 #define CLK_CEC_LSE 0x00009180 211 #define CLK_CEC_LSI 0x00009181 212 #define CLK_CEC_CSI_DIV122 0x00009182 213 #define CLK_CEC_DISABLED 0x00009183 214 215 #define CLK_USBPHY_HSE 0x000091C0 216 #define CLK_USBPHY_PLL4R 0x000091C1 217 #define CLK_USBPHY_HSE_DIV2 0x000091C2 218 #define CLK_USBPHY_DISABLED 0x000091C3 219 220 #define CLK_USBO_PLL4R 0x800091C0 221 #define CLK_USBO_USBPHY 0x800091C1 222 223 #define CLK_RNG1_CSI 0x00000CC0 224 #define CLK_RNG1_PLL4R 0x00000CC1 225 #define CLK_RNG1_LSE 0x00000CC2 226 #define CLK_RNG1_LSI 0x00000CC3 227 228 #define CLK_RNG2_CSI 0x00009200 229 #define CLK_RNG2_PLL4R 0x00009201 230 #define CLK_RNG2_LSE 0x00009202 231 #define CLK_RNG2_LSI 0x00009203 232 233 #define CLK_CKPER_HSI 0x00000D00 234 #define CLK_CKPER_CSI 0x00000D01 235 #define CLK_CKPER_HSE 0x00000D02 236 #define CLK_CKPER_DISABLED 0x00000D03 237 238 #define CLK_STGEN_HSI 0x00000D40 239 #define CLK_STGEN_HSE 0x00000D41 240 #define CLK_STGEN_DISABLED 0x00000D43 241 242 #define CLK_DSI_DSIPLL 0x00009240 243 #define CLK_DSI_PLL4P 0x00009241 244 245 #define CLK_ADC_PLL4R 0x00009280 246 #define CLK_ADC_CKPER 0x00009281 247 #define CLK_ADC_PLL3Q 0x00009282 248 #define CLK_ADC_DISABLED 0x00009283 249 250 #define CLK_LPTIM45_PCLK3 0x000092C0 251 #define CLK_LPTIM45_PLL4P 0x000092C1 252 #define CLK_LPTIM45_PLL3Q 0x000092C2 253 #define CLK_LPTIM45_LSE 0x000092C3 254 #define CLK_LPTIM45_LSI 0x000092C4 255 #define CLK_LPTIM45_CKPER 0x000092C5 256 #define CLK_LPTIM45_DISABLED 0x000092C7 257 258 #define CLK_LPTIM23_PCLK3 0x00009300 259 #define CLK_LPTIM23_PLL4Q 0x00009301 260 #define CLK_LPTIM23_CKPER 0x00009302 261 #define CLK_LPTIM23_LSE 0x00009303 262 #define CLK_LPTIM23_LSI 0x00009304 263 #define CLK_LPTIM23_DISABLED 0x00009307 264 265 #define CLK_LPTIM1_PCLK1 0x00009340 266 #define CLK_LPTIM1_PLL4P 0x00009341 267 #define CLK_LPTIM1_PLL3Q 0x00009342 268 #define CLK_LPTIM1_LSE 0x00009343 269 #define CLK_LPTIM1_LSI 0x00009344 270 #define CLK_LPTIM1_CKPER 0x00009345 271 #define CLK_LPTIM1_DISABLED 0x00009347 272 273 /* define for st,pll /csg */ 274 #define SSCG_MODE_CENTER_SPREAD 0 275 #define SSCG_MODE_DOWN_SPREAD 1 276 277 /* define for st,drive */ 278 #define LSEDRV_LOWEST 0 279 #define LSEDRV_MEDIUM_LOW 1 280 #define LSEDRV_MEDIUM_HIGH 2 281 #define LSEDRV_HIGHEST 3 282 283 #endif 284