1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef XLAT_TABLES_AARCH32_H 8 #define XLAT_TABLES_AARCH32_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 14 #if !defined(PAGE_SIZE) 15 #error "PAGE_SIZE is not defined." 16 #endif 17 18 /* 19 * In AArch32 state, the MMU only supports 4KB page granularity, which means 20 * that the first translation table level is either 1 or 2. Both of them are 21 * allowed to have block and table descriptors. See section G4.5.6 of the 22 * ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information. 23 * 24 * The define below specifies the first table level that allows block 25 * descriptors. 26 */ 27 #if PAGE_SIZE != PAGE_SIZE_4KB 28 #error "Invalid granule size. AArch32 supports 4KB pages only." 29 #endif 30 31 #define MIN_LVL_BLOCK_DESC U(1) 32 33 #define XLAT_TABLE_LEVEL_MIN U(1) 34 35 /* 36 * Define the architectural limits of the virtual address space in AArch32 37 * state. 38 * 39 * TTBCR.TxSZ is calculated as 32 minus the width of said address space. The 40 * value of TTBCR.TxSZ must be in the range 0 to 7 [1], which means that the 41 * virtual address space width must be in the range 32 to 25 bits. 42 * 43 * [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 44 * information, Section G4.6.5 45 */ 46 #define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(32) - TTBCR_TxSZ_MAX)) 47 #define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(32) - TTBCR_TxSZ_MIN)) 48 49 /* 50 * Here we calculate the initial lookup level from the value of the given 51 * virtual address space size. For a 4 KB page size, 52 * - level 1 supports virtual address spaces of widths 32 to 31 bits; 53 * - level 2 from 30 to 25. 54 * 55 * Wider or narrower address spaces are not supported. As a result, level 3 56 * cannot be used as the initial lookup level with 4 KB granularity. 57 * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 58 * information, Section G4.6.5 59 * 60 * For example, for a 31-bit address space (i.e. virt_addr_space_size == 61 * 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table 62 * G4-5 in the ARM ARM, the initial lookup level for an address space like that 63 * is 1. 64 * 65 * Note that this macro assumes that the given virtual address space size is 66 * valid. 67 */ 68 #define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_sz) \ 69 (((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) ? \ 70 U(1) : U(2)) 71 72 #endif /* XLAT_TABLES_AARCH32_H */ 73