1 /*
2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <bl31/interrupt_mgmt.h>
9 #include <common/bl_common.h>
10 #include <common/ep_info.h>
11 #include <lib/mmio.h>
12 #include <lib/xlat_tables/xlat_tables_v2.h>
13 #include <platform_def.h>
14 #include <stdint.h>
15
16 /*******************************************************************************
17 * Platform memory map regions
18 ******************************************************************************/
19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
20 AML_NSDRAM0_SIZE, \
21 MT_MEMORY | MT_RW | MT_NS)
22
23 #define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
24 AML_NSDRAM1_SIZE, \
25 MT_MEMORY | MT_RW | MT_NS)
26
27 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
28 AML_SEC_DEVICE0_SIZE, \
29 MT_DEVICE | MT_RW | MT_SECURE)
30
31 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
32 AML_SEC_DEVICE1_SIZE, \
33 MT_DEVICE | MT_RW | MT_SECURE)
34
35 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
36 AML_TZRAM_SIZE, \
37 MT_DEVICE | MT_RW | MT_SECURE)
38
39 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
40 AML_SEC_DEVICE2_SIZE, \
41 MT_DEVICE | MT_RW | MT_SECURE)
42
43 #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
44 AML_SEC_DEVICE3_SIZE, \
45 MT_DEVICE | MT_RW | MT_SECURE)
46
47 static const mmap_region_t gxbb_mmap[] = {
48 MAP_NSDRAM0,
49 MAP_NSDRAM1,
50 MAP_SEC_DEVICE0,
51 MAP_SEC_DEVICE1,
52 MAP_TZRAM,
53 MAP_SEC_DEVICE2,
54 MAP_SEC_DEVICE3,
55 {0}
56 };
57
58 /*******************************************************************************
59 * Per-image regions
60 ******************************************************************************/
61 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
62 BL31_END - BL31_BASE, \
63 MT_MEMORY | MT_RW | MT_SECURE)
64
65 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
66 BL_CODE_END - BL_CODE_BASE, \
67 MT_CODE | MT_SECURE)
68
69 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
70 BL_RO_DATA_END - BL_RO_DATA_BASE, \
71 MT_RO_DATA | MT_SECURE)
72
73 #define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
74 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
75 MT_DEVICE | MT_RW | MT_SECURE)
76
77 /*******************************************************************************
78 * Function that sets up the translation tables.
79 ******************************************************************************/
aml_setup_page_tables(void)80 void aml_setup_page_tables(void)
81 {
82 #if IMAGE_BL31
83 const mmap_region_t gxbb_bl_mmap[] = {
84 MAP_BL31,
85 MAP_BL_CODE,
86 MAP_BL_RO_DATA,
87 #if USE_COHERENT_MEM
88 MAP_BL_COHERENT,
89 #endif
90 {0}
91 };
92 #endif
93
94 mmap_add(gxbb_bl_mmap);
95
96 mmap_add(gxbb_mmap);
97
98 init_xlat_tables();
99 }
100
101 /*******************************************************************************
102 * Function that returns the system counter frequency
103 ******************************************************************************/
plat_get_syscnt_freq2(void)104 unsigned int plat_get_syscnt_freq2(void)
105 {
106 uint32_t val;
107
108 val = mmio_read_32(AML_SYS_CPU_CFG7);
109 val &= 0xFDFFFFFF;
110 mmio_write_32(AML_SYS_CPU_CFG7, val);
111
112 val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
113 val &= 0xFFFFFE00;
114 mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
115
116 return AML_OSC24M_CLK_IN_HZ;
117 }
118