1 /*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <common/fdt_wrappers.h>
9 #include <drivers/arm/gicv3.h>
10 #include <drivers/arm/gic_common.h>
11 #include <libfdt.h>
12
13 #include <platform_def.h>
14 #include <plat/common/platform.h>
15 #include <platform_def.h>
16
17 static const interrupt_prop_t fpga_interrupt_props[] = {
18 PLATFORM_G1S_PROPS(INTR_GROUP1S),
19 PLATFORM_G0_PROPS(INTR_GROUP0)
20 };
21
22 static uintptr_t fpga_rdistif_base_addrs[PLATFORM_CORE_COUNT];
23
fpga_mpidr_to_core_pos(unsigned long mpidr)24 static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr)
25 {
26 return (unsigned int)plat_core_pos_by_mpidr(mpidr);
27 }
28
29 static gicv3_driver_data_t fpga_gicv3_driver_data = {
30 .interrupt_props = fpga_interrupt_props,
31 .interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props),
32 .rdistif_num = PLATFORM_CORE_COUNT,
33 .rdistif_base_addrs = fpga_rdistif_base_addrs,
34 .mpidr_to_core_pos = fpga_mpidr_to_core_pos
35 };
36
plat_fpga_gic_init(void)37 void plat_fpga_gic_init(void)
38 {
39 const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
40 int node, ret;
41
42 node = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3");
43 if (node < 0) {
44 WARN("No \"arm,gic-v3\" compatible node found in DT, no GIC support.\n");
45 return;
46 }
47
48 /* TODO: Assuming only empty "ranges;" properties up the bus path. */
49 ret = fdt_get_reg_props_by_index(fdt, node, 0,
50 &fpga_gicv3_driver_data.gicd_base, NULL);
51 if (ret < 0) {
52 WARN("Could not read GIC distributor address from DT.\n");
53 return;
54 }
55
56 ret = fdt_get_reg_props_by_index(fdt, node, 1,
57 &fpga_gicv3_driver_data.gicr_base, NULL);
58 if (ret < 0) {
59 WARN("Could not read GIC redistributor address from DT.\n");
60 return;
61 }
62
63 gicv3_driver_init(&fpga_gicv3_driver_data);
64 gicv3_distif_init();
65 gicv3_rdistif_init(plat_my_core_pos());
66 gicv3_cpuif_enable(plat_my_core_pos());
67 }
68
fpga_pwr_gic_on_finish(void)69 void fpga_pwr_gic_on_finish(void)
70 {
71 gicv3_rdistif_init(plat_my_core_pos());
72 gicv3_cpuif_enable(plat_my_core_pos());
73 }
74
fpga_pwr_gic_off(void)75 void fpga_pwr_gic_off(void)
76 {
77 gicv3_cpuif_disable(plat_my_core_pos());
78 gicv3_rdistif_off(plat_my_core_pos());
79 }
80
fpga_get_nr_gic_cores(void)81 unsigned int fpga_get_nr_gic_cores(void)
82 {
83 return gicv3_rdistif_get_number_frames(fpga_gicv3_driver_data.gicr_base);
84 }
85