1 /* 2 * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include <drivers/auth/mbedtls/mbedtls_config.h> 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #include "../juno_def.h" 22 23 /* Required platform porting definitions */ 24 /* Juno supports system power domain */ 25 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 26 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 27 JUNO_CLUSTER_COUNT + \ 28 PLATFORM_CORE_COUNT) 29 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 30 JUNO_CLUSTER1_CORE_COUNT) 31 32 /* Cryptocell HW Base address */ 33 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 34 35 /* 36 * Other platform porting definitions are provided by included headers 37 */ 38 39 /* 40 * Required ARM standard platform porting definitions 41 */ 42 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 43 44 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 45 46 /* Use the bypass address */ 47 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 48 BL1_ROM_BYPASS_OFFSET) 49 50 #define NSRAM_BASE UL(0x2e000000) 51 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 52 53 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 54 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 55 56 #define PLAT_HW_CONFIG_DTB_BASE ULL(0x82000000) 57 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x00008000) /* 32KB */ 58 59 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 60 PLAT_HW_CONFIG_DTB_BASE, \ 61 PLAT_HW_CONFIG_DTB_SIZE, \ 62 MT_MEMORY | MT_RO | MT_NS) 63 64 /* virtual address used by dynamic mem_protect for chunk_base */ 65 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 66 67 /* 68 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 69 */ 70 71 #if USE_ROMLIB 72 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 73 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 74 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 75 #else 76 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 77 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 78 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 79 #endif 80 81 /* 82 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 83 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 84 * flash 85 */ 86 87 #if TRUSTED_BOARD_BOOT 88 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 89 #else 90 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 91 #endif /* TRUSTED_BOARD_BOOT */ 92 93 /* 94 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 95 * plat_arm_mmap array defined for each BL stage. 96 */ 97 #ifdef IMAGE_BL1 98 # define PLAT_ARM_MMAP_ENTRIES 7 99 # define MAX_XLAT_TABLES 4 100 #endif 101 102 #ifdef IMAGE_BL2 103 #ifdef SPD_opteed 104 # define PLAT_ARM_MMAP_ENTRIES 11 105 # define MAX_XLAT_TABLES 5 106 #else 107 # define PLAT_ARM_MMAP_ENTRIES 10 108 # define MAX_XLAT_TABLES 4 109 #endif 110 #endif 111 112 #ifdef IMAGE_BL2U 113 # define PLAT_ARM_MMAP_ENTRIES 5 114 # define MAX_XLAT_TABLES 3 115 #endif 116 117 #ifdef IMAGE_BL31 118 # define PLAT_ARM_MMAP_ENTRIES 7 119 # define MAX_XLAT_TABLES 5 120 #endif 121 122 #ifdef IMAGE_BL32 123 # define PLAT_ARM_MMAP_ENTRIES 6 124 # define MAX_XLAT_TABLES 4 125 #endif 126 127 /* 128 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 129 * plus a little space for growth. 130 */ 131 #if TRUSTED_BOARD_BOOT 132 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 133 #else 134 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 135 #endif 136 137 /* 138 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 139 * little space for growth. 140 */ 141 #if TRUSTED_BOARD_BOOT 142 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 143 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 144 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 145 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 146 #else 147 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 148 #endif 149 #else 150 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 151 #endif 152 153 /* 154 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 155 * calculated using the current BL31 PROGBITS debug size plus the sizes of 156 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 157 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 158 */ 159 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 160 161 #if JUNO_AARCH32_EL3_RUNTIME 162 /* 163 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 164 * calculated using the current BL32 PROGBITS debug size plus the sizes of 165 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 166 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 167 */ 168 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) 169 #endif 170 171 /* 172 * Size of cacheable stacks 173 */ 174 #if defined(IMAGE_BL1) 175 # if TRUSTED_BOARD_BOOT 176 # define PLATFORM_STACK_SIZE UL(0x1000) 177 # else 178 # define PLATFORM_STACK_SIZE UL(0x440) 179 # endif 180 #elif defined(IMAGE_BL2) 181 # if TRUSTED_BOARD_BOOT 182 # define PLATFORM_STACK_SIZE UL(0x1000) 183 # else 184 # define PLATFORM_STACK_SIZE UL(0x400) 185 # endif 186 #elif defined(IMAGE_BL2U) 187 # define PLATFORM_STACK_SIZE UL(0x400) 188 #elif defined(IMAGE_BL31) 189 # if PLAT_XLAT_TABLES_DYNAMIC 190 # define PLATFORM_STACK_SIZE UL(0x800) 191 # else 192 # define PLATFORM_STACK_SIZE UL(0x400) 193 # endif 194 #elif defined(IMAGE_BL32) 195 # define PLATFORM_STACK_SIZE UL(0x440) 196 #endif 197 198 /* 199 * Since free SRAM space is scant, enable the ASSERTION message size 200 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 201 */ 202 #define PLAT_LOG_LEVEL_ASSERT 40 203 204 /* CCI related constants */ 205 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 206 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 207 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 208 209 /* System timer related constants */ 210 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 211 212 /* TZC related constants */ 213 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 214 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 215 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 216 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 217 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 218 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 219 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 220 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 221 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 222 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 223 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 224 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 225 226 /* TZC related constants */ 227 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 228 229 /* 230 * Required ARM CSS based platform porting definitions 231 */ 232 233 /* GIC related constants (no GICR in GIC-400) */ 234 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 235 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 236 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 237 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 238 239 /* MHU related constants */ 240 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 241 242 /* 243 * Base address of the first memory region used for communication between AP 244 * and SCP. Used by the BOM and SCPI protocols. 245 */ 246 #if !CSS_USE_SCMI_SDS_DRIVER 247 /* 248 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 249 * means the SCP/AP configuration data gets overwritten when the AP initiates 250 * communication with the SCP. The configuration data is expected to be a 251 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 252 * which CPU is the primary, according to the shift and mask definitions below. 253 */ 254 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 255 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 256 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 257 #endif 258 259 /* 260 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 261 * anything else in this memory region and is handed over to the SCP before 262 * BL31 is loaded over the top. 263 */ 264 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 265 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 266 267 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 268 269 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 270 CSS_G1S_IRQ_PROPS(grp), \ 271 ARM_G1S_IRQ_PROPS(grp), \ 272 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 273 (grp), GIC_INTR_CFG_LEVEL), \ 274 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 275 (grp), GIC_INTR_CFG_LEVEL), \ 276 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 277 (grp), GIC_INTR_CFG_LEVEL), \ 278 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 279 (grp), GIC_INTR_CFG_LEVEL), \ 280 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 281 (grp), GIC_INTR_CFG_LEVEL), \ 282 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 283 (grp), GIC_INTR_CFG_LEVEL), \ 284 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 285 (grp), GIC_INTR_CFG_LEVEL), \ 286 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 287 (grp), GIC_INTR_CFG_LEVEL) 288 289 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 290 291 /* 292 * Required ARM CSS SoC based platform porting definitions 293 */ 294 295 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 296 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 297 298 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 299 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 300 301 /* System power domain level */ 302 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 303 304 /* 305 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 306 */ 307 #ifdef __aarch64__ 308 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 309 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 310 #else 311 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 312 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 313 #endif 314 315 /* Number of SCMI channels on the platform */ 316 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 317 318 #endif /* PLATFORM_DEF_H */ 319