1#
2# Copyright (c) 2020, Arm Limited. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7MORELLO_BASE		:=	plat/arm/board/morello
8
9INTERCONNECT_SOURCES	:=	${MORELLO_BASE}/morello_interconnect.c
10
11PLAT_INCLUDES		:=	-I${MORELLO_BASE}/include
12
13MORELLO_CPU_SOURCES	:=	lib/cpus/aarch64/rainier.S
14
15# GIC-600 configuration
16GICV3_SUPPORT_GIC600	:=	1
17
18# Include GICv3 driver files
19include drivers/arm/gic/v3/gicv3.mk
20
21MORELLO_GIC_SOURCES	:=	${GICV3_SOURCES}			\
22				plat/common/plat_gicv3.c		\
23				plat/arm/common/arm_gicv3.c		\
24
25PLAT_BL_COMMON_SOURCES	:=	${MORELLO_BASE}/morello_plat.c		\
26				${MORELLO_BASE}/aarch64/morello_helper.S
27
28BL31_SOURCES		:=	${MORELLO_CPU_SOURCES}			\
29				${INTERCONNECT_SOURCES}			\
30				${MORELLO_GIC_SOURCES}			\
31				${MORELLO_BASE}/morello_bl31_setup.c	\
32				${MORELLO_BASE}/morello_topology.c	\
33				${MORELLO_BASE}/morello_security.c	\
34				drivers/arm/css/sds/sds.c
35
36FDT_SOURCES		+=	fdts/morello-fvp.dts
37
38# TF-A not required to load the SCP Images
39override CSS_LOAD_SCP_IMAGES		:=	0
40
41# BL1/BL2 Image not a part of the capsule Image for morello
42override NEED_BL1			:=	no
43override NEED_BL2			:=	no
44override NEED_BL2U			:=	no
45
46#TF-A for morello starts from BL31
47override RESET_TO_BL31			:=	1
48
49# 32 bit mode not supported
50override CTX_INCLUDE_AARCH32_REGS	:=	0
51
52override ARM_PLAT_MT			:=	1
53
54# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
55# SCP during power management operations and for SCP RAM Firmware transfer.
56CSS_USE_SCMI_SDS_DRIVER			:=	1
57
58# System coherency is managed in hardware
59HW_ASSISTED_COHERENCY			:=	1
60
61# When building for systems with hardware-assisted coherency, there's no need to
62# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
63USE_COHERENT_MEM			:=	0
64
65include plat/arm/common/arm_common.mk
66include plat/arm/css/common/css_common.mk
67include plat/arm/board/common/board_common.mk
68