1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 12 #include <sgi_soc_platform_def_v2.h> 13 14 #if (CSS_SGI_PLATFORM_VARIANT == 1) 15 #define PLAT_ARM_CLUSTER_COUNT U(8) 16 #else 17 #define PLAT_ARM_CLUSTER_COUNT U(16) 18 #endif 19 20 #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1) 21 #define CSS_SGI_MAX_PE_PER_CPU U(1) 22 23 #define PLAT_CSS_MHU_BASE UL(0x2A920000) 24 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 25 26 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 27 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 28 29 /* TZC Related Constants */ 30 #define PLAT_ARM_TZC_BASE UL(0x10720000) 31 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 32 33 #define TZC400_OFFSET UL(0x1000000) 34 35 #if (CSS_SGI_PLATFORM_VARIANT == 1) 36 #define TZC400_COUNT U(2) 37 #else 38 #define TZC400_COUNT U(8) 39 #endif 40 41 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 42 (n * TZC400_OFFSET)) 43 44 #define TZC_NSAID_ALL_AP U(0) 45 #define TZC_NSAID_PCI U(1) 46 #define TZC_NSAID_HDLCD0 U(2) 47 #define TZC_NSAID_DMA U(5) 48 #define TZC_NSAID_DMA2 U(8) 49 #define TZC_NSAID_CLCD U(7) 50 #define TZC_NSAID_AP U(9) 51 #define TZC_NSAID_VIRTIO U(15) 52 53 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 54 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \ 55 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \ 56 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \ 57 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA)) | \ 58 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA2)) | \ 59 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \ 60 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ 61 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) 62 63 /* 64 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 65 */ 66 #ifdef __aarch64__ 67 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) 68 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) 69 #else 70 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 71 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 72 #endif 73 74 /* GIC related constants */ 75 #define PLAT_ARM_GICD_BASE UL(0x30000000) 76 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 77 78 #if (CSS_SGI_PLATFORM_VARIANT == 1) 79 #define PLAT_ARM_GICR_BASE UL(0x30100000) 80 #else 81 #define PLAT_ARM_GICR_BASE UL(0x301C0000) 82 #endif 83 84 #endif /* PLATFORM_DEF_H */ 85