1 /* 2 * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <sgi_soc_platform_def.h> 12 13 #define PLAT_ARM_CLUSTER_COUNT U(4) 14 #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1) 15 #define CSS_SGI_MAX_PE_PER_CPU U(1) 16 17 #define PLAT_CSS_MHU_BASE UL(0x45400000) 18 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 19 20 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 21 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 22 23 /* TZC Related Constants */ 24 #define PLAT_ARM_TZC_BASE UL(0x21830000) 25 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 26 (n * TZC400_OFFSET)) 27 #define TZC400_OFFSET UL(0x1000000) 28 #define TZC400_COUNT U(8) 29 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 30 31 #define TZC_NSAID_ALL_AP U(0) 32 #define TZC_NSAID_PCI U(1) 33 #define TZC_NSAID_HDLCD0 U(2) 34 #define TZC_NSAID_CLCD U(7) 35 #define TZC_NSAID_AP U(9) 36 #define TZC_NSAID_VIRTIO U(15) 37 38 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 39 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \ 40 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \ 41 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \ 42 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \ 43 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ 44 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) 45 46 /* Virtual address used by dynamic mem_protect for chunk_base */ 47 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) 48 49 /* Physical and virtual address space limits for MMU in AARCH64 mode */ 50 #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ 51 CSS_SGI_CHIP_COUNT) 52 #define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ 53 CSS_SGI_CHIP_COUNT) 54 55 /* GIC related constants */ 56 #define PLAT_ARM_GICD_BASE UL(0x30000000) 57 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 58 #define PLAT_ARM_GICR_BASE UL(0x30140000) 59 60 #endif /* PLATFORM_DEF_H */ 61