1# Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
2#
3# SPDX-License-Identifier: BSD-3-Clause
4#
5
6# Enable GICv4 extension with multichip driver
7GIC_ENABLE_V4_EXTN		:=	1
8GICV3_IMPL_GIC600_MULTICHIP	:=	1
9
10include plat/arm/css/sgi/sgi-common.mk
11
12RDV1MC_BASE	=	plat/arm/board/rdv1mc
13
14PLAT_INCLUDES		+=	-I${RDV1MC_BASE}/include/
15
16SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_v1.S
17
18PLAT_BL_COMMON_SOURCES	+=	${CSS_ENT_BASE}/sgi_plat.c
19
20BL1_SOURCES		+=	${SGI_CPU_SOURCES}			\
21				${RDV1MC_BASE}/rdv1mc_err.c
22
23BL2_SOURCES		+=	${RDV1MC_BASE}/rdv1mc_plat.c	\
24				${RDV1MC_BASE}/rdv1mc_security.c	\
25				${RDV1MC_BASE}/rdv1mc_err.c	\
26				drivers/arm/tzc/tzc400.c	\
27				plat/arm/common/arm_tzc400.c	\
28				lib/utils/mem_region.c			\
29				plat/arm/common/arm_nor_psci_mem_protect.c
30
31BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
32				${RDV1MC_BASE}/rdv1mc_plat.c	\
33				${RDV1MC_BASE}/rdv1mc_topology.c	\
34				drivers/cfi/v2m/v2m_flash.c		\
35				drivers/arm/gic/v3/gic600_multichip.c	\
36				lib/utils/mem_region.c			\
37				plat/arm/common/arm_nor_psci_mem_protect.c
38
39ifeq (${TRUSTED_BOARD_BOOT}, 1)
40BL1_SOURCES		+=	${RDV1MC_BASE}/rdv1mc_trusted_boot.c
41BL2_SOURCES		+=	${RDV1MC_BASE}/rdv1mc_trusted_boot.c
42endif
43
44# Enable dynamic addition of MMAP regions in BL31
45BL31_CFLAGS		+=	-DPLAT_XLAT_TABLES_DYNAMIC
46
47# Add the FDT_SOURCES and options for Dynamic Config
48FDT_SOURCES		+=	${RDV1MC_BASE}/fdts/${PLAT}_fw_config.dts	\
49				${RDV1MC_BASE}/fdts/${PLAT}_tb_fw_config.dts
50FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
51TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
52
53# Add the FW_CONFIG to FIP and specify the same to certtool
54$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
55# Add the TB_FW_CONFIG to FIP and specify the same to certtool
56$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
57
58$(eval $(call CREATE_SEQ,SEQ,4))
59ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
60 $(error  "Chip count for RD-V1-MC should be either $(SEQ) \
61 currently it is set to ${CSS_SGI_CHIP_COUNT}.")
62endif
63
64FDT_SOURCES		+=	${RDV1MC_BASE}/fdts/${PLAT}_nt_fw_config.dts
65NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
66
67# Add the NT_FW_CONFIG to FIP and specify the same to certtool
68$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
69
70override CTX_INCLUDE_AARCH32_REGS	:= 0
71override ENABLE_AMU			:= 1
72
73ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
74 $(error "CSS_SGI_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
75     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
76endif
77