1/* 2 * Copyright (c) 2020-21, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/memory/memory.h> 10 11#define MODE_EL0 (0x0) 12#define MODE_EL1 (0x1) 13#define MODE_EL2 (0x2) 14 15/ { 16 compatible = "arm,ffa-manifest"; 17 18 /* 19 * Size is defining the boundary for area, which will be reserved in 20 * Secure Partition memory region to store StandAloneMM(StMM) boot 21 * data. In this area StMM boot data will be copied from DTS config, 22 * for successful StMM booting. 23 */ 24 configsize { 25 compatible = "config-size"; 26 size = <0x1000>; 27 }; 28 29 /* 30 * Following booting parameters are used by StandAloneMM 31 * during it's booting. 32 * Earlier this boot data information was part of plat 33 * specific file. Now this boot parameters are captured in this 34 * fw_config file, and address of the fw_config is passed to 35 * StMM as booting argument. 36 */ 37 bootarg { 38 compatible = "bootargs"; 39 h_type = <0x7>; 40 h_version = <0x1>; 41 h_size = <128>; 42 h_attr = <0>; 43 sp_mem_base = <0x00000000 0xFF200000>; 44 sp_mem_limit = <0x00000000 0xFFC00000>; 45 sp_image_base = <0x00000000 0xFF200000>; 46 sp_stack_base = <0x00000000 0xFF640000>; 47 sp_heap_base = <0x00000000 0xFF650000>; 48 sp_ns_comm_buf_base = <0x00000000 0xFF600000>; 49 sp_shared_buf_base = <0x00000000 0xFF500000>; 50 sp_image_size = <0x00000000 0x300000>; 51 sp_pcpu_stack_size = <0x00000000 0x2000>; 52 sp_heap_size = <0x00000000 0x5B0000>; 53 sp_ns_comm_buf_size = <0x00000000 0x10000>; 54 sp_shared_buf_size = <0x00000000 0x100000>; 55 num_sp_mem_regions = <0x6>; 56 num_cpus = <0x8>; 57 }; 58 59 /* 60 * FF-A compatible Secure Partition Manager parses the 61 * config file and fetch the following booting arguments to 62 * pass on to StandAloneMM(StMM) Secure Partition. 63 * arg0 : Buffer base which is shared between EL3 and S-EL0. 64 * arg1 : Shared Buffer size. 65 * arg2 : TOS_FW_CONFIG address. 66 */ 67 ffa-config { 68 compatible = "ffa-configs"; 69 partition_id = <0x1>; 70 sp_arg0 = <0x0 0xff500000>; 71 sp_arg1 = <0x0 0x100000>; 72 sp_arg2 = <0x0 0x4001500>; 73 load_address = <0x0 0xff200000>; 74 stack_base = <0x0 0xff640000>; 75 stack_size = <0x0 0x2000>; 76 77 runtime-el = <MODE_EL0>; 78 }; 79 80 mem-regions { 81 compatible = "mem-regions"; 82 #address-cells = <2>; 83 #size-cells = <2>; 84 85 /* 86 * System registers region for access from S-EL0. 87 * Similar to PLAT_ARM_SECURE_MAP_SYSTEMREG. 88 */ 89 mem-region@1 { 90 reg = <0x0 0x1C010000 0x0 0x00010000>; 91 mem_region_type = <MEM_DEVICE>; 92 mem_region_secure = <MEM_SECURE>; 93 mem_region_access = <MEM_RW>; 94 granularity = <0x40000000>; 95 }; 96 97 /* 98 * ARM CSS SoC Peripherals and PCIe expansion area. 99 * Similar to SOC_CSS_MAP_DEVICE. 100 */ 101 mem-region@2 { 102 reg = <0x0 0x40000000 0x0 0x40000000>; 103 mem_region_type = <MEM_DEVICE>; 104 mem_region_secure = <MEM_SECURE>; 105 mem_region_access = <MEM_RW>; 106 granularity = <0x40000000>; 107 }; 108 109 /* 110 * SPM Payload memory. Mapped as code region for S-EL0 111 * Similar to ARM_SP_IMAGE_MMAP. 112 */ 113 mem-region@3 { 114 reg = <0x0 0xff200000 0x0 0x00300000>; 115 mem_region_type = <MEM_NORMAL>; 116 mem_region_secure = <MEM_SECURE>; 117 mem_region_access = <MEM_CODE>; 118 granularity = <0x1000>; 119 }; 120 121 /* 122 * Memory shared between EL3 and S-EL0. 123 * Similar to ARM_SPM_BUF_EL0_MMAP. 124 */ 125 mem-region@4 { 126 reg = <0x0 0xff500000 0x0 0x00100000>; 127 mem_region_type = <MEM_NORMAL>; 128 mem_region_secure = <MEM_SECURE>; 129 mem_region_access = <MEM_RO_DATA>; 130 granularity = <0x1000>; 131 }; 132 133 /* 134 * Memory shared between Normal world and S-EL0. 135 * Similar to ARM_SP_IMAGE_NS_BUF_MMAP. 136 */ 137 mem-region@5 { 138 reg = <0x0 0xff600000 0x0 0x00010000>; 139 mem_region_type = <MEM_NORMAL>; 140 mem_region_secure = <MEM_NON_SECURE>; 141 mem_region_access = <MEM_RW_DATA>; 142 granularity = <0x1000>; 143 }; 144 145 /* 146 * CPER buffer memory. 147 * Similar to CSS_SGI_SP_CPER_BUF_MMAP. 148 */ 149 mem-region@6 { 150 reg = <0x0 0xff610000 0x0 0x00020000>; 151 mem_region_type = <MEM_NORMAL>; 152 mem_region_secure = <MEM_SECURE>; 153 mem_region_access = <MEM_RW_DATA>; 154 granularity = <0x1000>; 155 }; 156 157 /* 158 * Secure Partition Stack region. 159 */ 160 mem-region@7 { 161 reg = <0x0 0xff630000 0x0 0x005d0000>; 162 mem_region_type = <MEM_NORMAL>; 163 mem_region_secure = <MEM_SECURE>; 164 mem_region_access = <MEM_RW_DATA>; 165 granularity = <0x1000>; 166 }; 167 168 /* 169 * Firmware config region. 170 */ 171 mem-region@8 { 172 reg = <0x0 0x4001000 0x0 0x0004000>; 173 mem_region_type = <MEM_NORMAL>; 174 mem_region_secure = <MEM_SECURE>; 175 mem_region_access = <MEM_RO_DATA>; 176 granularity = <0x1000>; 177 }; 178 179 /* 180 * NOR2 Flash region, used for Secure booting. 181 */ 182 mem-region@9 { 183 reg = <0x0 0x10000000 0x0 0x04000000>; 184 mem_region_type = <MEM_DEVICE>; 185 mem_region_secure = <MEM_SECURE>; 186 mem_region_access = <MEM_RW>; 187 granularity = <0x40000000>; 188 }; 189 }; 190}; 191